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ASIC simulation vs FPGA

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no_mad

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Hi,

I had this argument with my colleague. The argument is if any designs were verified on FPGA board, it must verify again on ASIC simulation tool with SDF file. This is to confirm the design will work without any bug or glitches when tape-out later.

According to my colleague, if the design is working on FPGA board. Thus, it definitely will work on ASIC. But my argument is what about delay and glitches. Since, these two (ASIC n FPGA) has a different architecture. As we all know, FPGA is a PLA and ASIC is gate.

I understand that FPGA is a good way to verify and confirm your algorithm.

Please share your opinion, highly appreciated.

Thanks in advance,
-no_mad
 

stevepre

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Your colleague is mostly right, but of course, you need to make sure the timing constraint must be good and verfied.

Glitches and delay?
Delay can be caught in timing analysis (STA).
Glitches? Glitches are everywhere in every design. And there are glitches in both FPGA and ASIC. But as long as it's synchronous design and it meets the timing, it will work.
 

ami

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Hi,
My recent taped-out chip is verified both by FPGA board & simulation (rtl & gate level), and here are some of my experiences:

1. by verifying your code on FPGA board, you may make sure that your chip functions well. There are some features require a very long time to be checked by RTL simulation, and FPGA is the only choice.

2. except using the FPGA--direct-->ASIC tecnology, verify the gate/timing with SDF file is a MUST. The problem here is not the function but the timing.

3. I feel, any code that carefully checked by RTL simulation--->run well in FPGA board +++ SDF timing check OK ---> ASIC chip will function OK.

rgrds,
 

bajahaya

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Hi,

It is not neccessary that a chip should funtionaly work well in ASIC if it is proven in FPGA design.

Reason:

FPGA routing are constraint driven routing,It means it has its structure already and only we short-circuit the interconnects to make each CLB to be connected. In contrast ASIC has a differnt routing topology.

FPGA mapping is done for respective architecuture and it can use more area hence more delay as well,ASIC in turn might have less area and less delay so data arrival might be early too.

In ASIC we have good control on timing requirements and tools available today are quite smart in opmitization,which is are there in FPGA.So we can assure if a design in proven in FPGA will work the same in ASIC. We should always go in design flow for STA and Paristic extraction of wires to know real-dealy and also to ensure the logic/functions in Verification.


Regards,
ALI
 

SkyHigh

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no_mad,

FPGA is a rapid prototyping fabric. You use it to verify that the FUNCTIONALITY of your RTL design works.

Rule of thumb: Always correct something at the top before you come down to the bottom.

From ASIC point of view, you must pass STA after post-synthesis before you proceed to floorplan.

Experience: You may pass STA after post-synthesis, but you may not pass post-layout simulation with SDF.

What's the difference: ASIC design is an art. FPGA design is a toy.

If you can do ASIC, you can do FPGA. But not vice-versa.
 

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