no_mad
Full Member level 5
Hi,
I had this argument with my colleague. The argument is if any designs were verified on FPGA board, it must verify again on ASIC simulation tool with SDF file. This is to confirm the design will work without any bug or glitches when tape-out later.
According to my colleague, if the design is working on FPGA board. Thus, it definitely will work on ASIC. But my argument is what about delay and glitches. Since, these two (ASIC n FPGA) has a different architecture. As we all know, FPGA is a PLA and ASIC is gate.
I understand that FPGA is a good way to verify and confirm your algorithm.
Please share your opinion, highly appreciated.
Thanks in advance,
-no_mad
I had this argument with my colleague. The argument is if any designs were verified on FPGA board, it must verify again on ASIC simulation tool with SDF file. This is to confirm the design will work without any bug or glitches when tape-out later.
According to my colleague, if the design is working on FPGA board. Thus, it definitely will work on ASIC. But my argument is what about delay and glitches. Since, these two (ASIC n FPGA) has a different architecture. As we all know, FPGA is a PLA and ASIC is gate.
I understand that FPGA is a good way to verify and confirm your algorithm.
Please share your opinion, highly appreciated.
Thanks in advance,
-no_mad