ASIC Design = Physical Design.......

[gandhipathik]

Hello everyone.

which parameters affect the design timing? can anyone explain?


Thanks-

 

[sagar.m]

Hi
According to my knowledge the parameter which effect the design timing is the design library which you are using for synthesis of your design because it specify the delay of various component used in your design and is technology dependent so some technology may have component or design micro which will take less or more delay as compare to the same component of the other technology library, along with that it also depend your RTL code which specify in component your design is going to synthesize more no. of combinational or sequential logic , no. of latches etc.

please somebody tell am i correct or not ?
Thank you

- - - Updated - - -

Hi
According to my knowledge the parameter which effect the design timing is the design library which you are using for synthesis of your design because it specify the delay of various component used in your design and is technology dependent so some technology may have component or design micro which will take less or more delay as compare to the same component of the other technology library, along with that it also depend your RTL code which specify in component your design is going to synthesize more no. of combinational or sequential logic , no. of latches etc.

please somebody tell am i correct or not ?
Thank you