ASIC Design Libraries

[subhash_chevella]

Hello all,

While doing Synthesis and Timing analysis using DC and PT we will use Worst Case libraries.
At the time of Fabrication which library will be used and why?

thanks,
Subhash

 

[kornukhin]

Worst Case library used to analyze setup violations for worst operating conditions (to be sure that design still be working in such case).
Worst/best/typical libraries contain different timing information for the same model of silicon (GaAs...), which will be fabricated.

 

[subhash_chevella]

Hi,
I got your point.
My question is with respect to which library they will fabricate the chip?

 

[oratie]

The FAB deliver to customers (IP/Lib developers) spice model of transistors in three corners Fast, Typical and Slow (Fast mean smallest delay). The FAB guarantee, that the most chips(wafers) will contain transistors with parameters equal to Typical, bust some chips (wafers) may contain transistors with parameters between Fast and Slow (it's real life). Then IP developer is characterize (measure parameters) their IP/Lib schematic in different condition (usually it is Typ_transistor+Typ_temperatur+Typ_voltage, Slow_tran+High_temp+low_volt, Fast_tran+Low_temp+High_volt, these conditions are correspond to typical_delay, biggest_delay and smallest_delay). In order to be sure, that your design is working at different temps, different volts, you should check your timing in different conditions. And FAB will try(only try) to fabricate your chip with Typical parameters of transistors. Still, it's real life, that your chips will be fabricated with parameters between Fast and Slow (not equal to Typ).

 

[subhash_chevella]

hi oratie,

thanks a lot..

regards,
Subhash