asic design flow........

[gandhipathik]

What is floorplanning??
what are the steps to do floorplanning by using Xilinx ISE?

 

[rca]

Xilinx is a FPGA tool, no relation with ASIC flow, no?

 

[sharif.shiek]

XILINX is FPGA...so you can't use that for ASIC

 

[gandhipathik]

so how to do floorplan? i.e. what are the steps to do floorplan?

 

[sharif.shiek]

so how to do floorplan? i.e. what are the steps to do floorplan?

floor plan mainly defines the periphery and core areas and I/O pads locations and place known macros all standard cells..

1)in floor plan first create physical only cells, which are not present in net list (say pad cells, corner cells, filler cells).
2)now specify the pad locations.
3)after that we have to initialize the floor plan, in floor plan initialization we define core area and place pad cells
4)after initialization we have to place filler cells for N-well & P-well continuity
5)next define power P/G connections
6)then specify ignored routing layers
7)now place all known macros
8)now define placement blockages
9)now specify virtual flat placement strategies like specifying sliver (narrow channel between macros) size and turn on of virtual in placement optimization
10)now perform virtual flat placement, means placing all unknown macros and standard cells
11)now analyze the congestion and if found any congestion do the following
if it is cell congestion then distribute the cells by defining the utilization factor and if it routing congestion then change the macro constraints and macro blockages (keep out margins) and change placement strategies and perform congestion driven placement with medium effort algorithms
12)now again analyze and if found any congestion then perform the congestion driven placement with high effort algorithms
13)now analyze the congestion and if again found congestion then change the floor plan
14)if congestion is resolved then save the cell (.def file)


is it helpful?

cheers