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Yield in VLSI says that the amount of appreciable outcome after designing the ASIC chip.
Something like if 100 chips are fabricated only 90 pass the tests and prove to be successfully functioning in all regards. the other 10 are considered as yield loss.
So during ASIC testing when technology keeps scaling down the interconnects between metal layers degrade the yield.
As we move into lower nano metre regime the yield loss will be more.
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