[SOLVED] ASIC Cell Library for Leonardo spectrum

[socboy]

Can any help me to find ASIC cell libraries ??.

I want to synthesize my VHDL code in Leonardo spectrum using ASIC libraries, but id not find any !!

Please help,

socboy

 

[cyteng]

TSMC35 library (typical)

Uploaded file: **broken link removed**

 

[cyteng]

fast

Uploaded file: **broken link removed**

 

[cyteng]

slow

Uploaded file: **broken link removed**

 

[palq]

Please help if any has ASIC cell library with verilog code.

 

[cnz]

me too!

Who can give me the library in .V format?

Thanks!

 

[marsgod]

Maybe you can use X-HDL convert the VHDL into Verilog.
But I think there is no delay info in the VHDL file.....

On 2002-04-12 05:27, palq wrote:
Please help if any has ASIC cell library with verilog code.

 

[socboy]

Cyteng,

thanks so much

 

[marsgod]

I found that there is a .syn in the package.
But I use syn@psys DC only, how can I convert this .syn into .lib or .db?
any suggestion?
thanks.

or Cyteng can post the .lib and .db files?
thanks anyway.

 

[steve88]

For Leonardo users targeting ASIC technology, try here:
**broken link removed**

But frankly speaking, do you think it is a good idea using Leonardo for ASIC synthesis?

steve88

 

[whatever]

syn to db

library compiler
import the .syn file -> write out the .db file

 

[marsgod]

Re: syn to db

I bring up the Lib Compiler GUI, but there is no a menu named "import"
,
only "Read" menu.
But when I try to read_lib the Mentor's syn file, a error occure.
Does the synopsys lib compiler can translate the .syn to .db file?

library compiler
import the .syn file -> write out the .db file

 

[farmerwang]

try TSMC & UMC website

U can try the TSMC & UMC website, their technology library is avaiable in db format

 

[srisrisri]

i have a doubt to share with you all...

we can convert .syn file to .db by using library compiler.
but how can we get .syn or .lib file from .db?
is there any tool to do this? if so please share with us or pm me

thanks anyway!

SSS