ASIC Backend- Custom layout Engineer in Bangalore&Hyderabad

BASIC:
Expertise in Custom Layout Standard Cells, I/O or special analog designs such as RF transceievers, LNA, VGA, PLL, DLL, LDO, Bandgap, VCO, ADC,DAC
Strong Layout Design Concepts
Experience in Pcell development
Experience in Layout Design tools such as Virtuoso, Virtuoso-XL
Expertise in SKILL Programming Language
Experience in Physical verification

DESIRED:
Exposure to Calibre, Hercules and Assura
Exposure to digital place & route
Basic understanding of Analog Design
Strong basics in process technology, fabrication techniques

Interested candidates please share your updated resume to prathap@fusionservices.in and also call us +91-80-32488880.

Hi,

I am Shareef Shiek B.tech (2011,ECE), looking for job in VLSI physical design even I have undergone PG DIPLOMA training to seek a challenging career and growth oriented position in the field of ASIC design and to work on challenging projects.I have strong knowledge on advanced digital design,CMOS Fundamentals, SoC Fundamentals, Floorplanning, Placement, Clock Tree Synthesis, Routing, Optimization, Parasitic Extraction, Static Timing Analysis, Physical Verification, Chip finishing. verilog HDL, C language, Cshell, TCL, PERL and I have done projects based on verilog HDL using XILINX ISE 9.2i simulator and RISC full chip with instance count of 60K and 15 macros at 90 nm technology using IC COMPILER.

Engineering Degree: B.Tech (Electronics and Communication Engineering)
Name of University: Jawaharlal Nehru technological University, Hyderabad
GPA Scores: 70%
Current Co: fresher with 6 months training experience in VLSI Physical Design
CTC Details: 0.0 lac
Notice Period: One week
Email : sharif.shiek@gmail.com


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Thanks & Regards..

Shareef Shiek..