ASCII decoder problem....RS-232 communication

[peter_88]

Hi guys

Actually we were suppose to do data communication through RS-232 this involved the exploitation of (UART) to set up a serial communication connection between the FPGA boards to a Personal Computer (PC) through a RS-232.

I managed to make a working UART code, the main problem is with the ASCII decoder. It should work in the following way
A system which receives ASCII codes from the PC through the serial ports, and send the translated message back to PC. The translated information is performed using a ASCII decoder, which will be designed in VHDL. Table below shows the translated message that will be sent for every ASCII code received.



and below is the general picture of communication btwn FPGA board and PC




If u guys have any code for ASII decoder plz post it here.

Thanks

 

[Kepsz]

U want using the complete ascii character set?

In my pc <-> fpga communication (transmitting numbers only in both ways), I'm using a bin -> bcd converter, then i'm simply add 11000 (48 in decimal) to the bcd numbers. If u intrested, i can post the code.


Btw, i do not recommend for you to use Windows in PC while u doing the developement. It can trick you. I have found some bugs in Win7's rts/cts handshaking. Even the wrong code worked under Windows which makes me thing my code is works good...

 

[peter_88]

U want using the complete ascii character set?

In my pc <-> fpga communication (transmitting numbers only in both ways), I'm using a bin -> bcd converter, then i'm simply add 11000 (48 in decimal) to the bcd numbers. If u intrested, i can post the code.


Btw, i do not recommend for you to use Windows in PC while u doing the developement. It can trick you. I have found some bugs in Win7's rts/cts handshaking. Even the wrong code worked under Windows which makes me thing my code is works good...

Can u plz post the code. It will be really helpful

 

[gongdori]

I would do it using FIFOs on both TX and RX side. When FIFO is not empty, you can get a ASCII code from RX FIFO, determine what you need to transmit and queue the characters to be transmitted on the TX FIFO. ASCII decoder can be implemented using a simple case statement in VHDL.

 

[Kepsz]

This code works up to 12 bit binary vectors.

library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.NUMERIC_STD.ALL;
*
entity bin_bcd is
	port (
			CLK_IN	:	in STD_LOGIC;
			INPUT		:	in STD_LOGIC_VECTOR (11 downto 0);
			OUTPUT	:	out STD_LOGIC_VECTOR (15 downto 0));
end bin_bcd;

architecture bin_bcd of bin_bcd is
	signal TEMP_BCD: STD_LOGIC_VECTOR(11 downto 0);
begin
bcd: process(CLK_IN, INPUT)
	variable MATH: unsigned(28 downto 0);
begin
	if (RISING_EDGE(CLK_IN)) then
		TEMP_BCD(11 downto 0) <= INPUT(11 downto 0);
		MATH(28 downto 0) := unsigned("00000000000000000" & TEMP_BCD);
		for i in 0 to 12 loop
			if MATH(16 downto 13) > "0100" then	
				MATH(16 downto 13) := MATH(16 downto 13) + "0011";
			end if;
			if MATH(20 downto 17) > "0100" then	
				MATH(20 downto 17) := MATH(20 downto 17) + "0011";
			end if;
			if MATH(24 downto 21) > "0100" then	
				MATH(24 downto 21) := MATH(24 downto 21) + "0011";
			end if;
			if MATH(28 downto 25) > "0100" then	
				MATH(28 downto 25) :=  MATH(28 downto 25) + "0011";
			end if;
			MATH(28 downto 1) := MATH(27 downto 0);
		end loop;
		OUTPUT(15 downto 0) <= std_logic_vector(MATH(28 downto 13));
	end if;
	end process bcd;
end bin_bcd;

 

[peter_88]

I would do it using FIFOs on both TX and RX side. When FIFO is not empty, you can get a ASCII code from RX FIFO, determine what you need to transmit and queue the characters to be transmitted on the TX FIFO. ASCII decoder can be implemented using a simple case statement in VHDL.

Do you have any ASCII decoder code that will fit the requirements of my question?? Plz help!!

 

[gongdori]

Sorry, Peter. I don't have any code now. But, it wouldn't be too bad to implement.
You can make a FSM which polls the RX FIFO empty flag. When it is not empty, you can dequeue one character from it, determine what that is and enqueue decoded characters to the TX FIFO...
You can repeat it until the RX FIFO is empty.