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array of vector in verilog.

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krishanu007

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In verilog I wrote it as
reg [7:0] acc [7:0];

now if I write acc[3] it actually refers 8 bit.
But if I write acc[3:2] what it actually refers

1. it refers 2 bit only.
2. It refers 16 bit (as intended by me)

????????
 

blooz

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In verilog I wrote it as
reg [7:0] acc [7:0];

now if I write acc[3] it actually refers 8 bit.
But if I write acc[3:2] what it actually refers

1. it refers 2 bit only.
2. It refers 16 bit (as intended by me)

????????

integer a[1:10]
a[3:5] is illegal.

You can not access an entire array.
You can not access a slice of an array.



h**p://www.cs.umbc.edu/portal/help/VHDL/verilog/types.html#arrays
 

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