array multiplier of 2 vector of 8 bit size.

[prashanthi999]

hai everyone im doing an array multiplication of 2 vector whose size is 8 bit , im getting error called index type which means not using similar type!! even though using same type for the vectors
how to deal it? there are 2 errors after counter process in my progrm.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity dot_product is
  port( a,b : in std_logic_vector (7 downto 0);
          clk,reset : in std_logic;
	  result : out std_logic_vector (15 downto 0)
       );
end dot_product;

architecture Behavioral of dot_product is

signal i : std_logic_vector(2 downto 0);
signal ai,bi :std_logic_vector (7 downto 0);
signal product,add_in,sum,accumulator  :std_logic_vector(15 downto 0);

 subtype sig8 is std_logic_vector (7 downto 0);
 
 
 type sig8_vector is array ( natural range <>) of sig8;

begin

control : process
begin
wait until rising_edge(clk);
if reset ='1' then
  i<= (others => '0');
else
  i<=i+1;
end if;
end process;

a_mux : ai <= a( std_logic_vector (i));////error here
b_mux : bi <= b( std_logic_vector (i)); /// error here

multiply : product <=ai* bi;
zero_mux : add_in <=x"0000" when i = 0 else accumulator;
 add : sum <=product +add_in;
 
 accumulate : process
 begin
 wait until rising_edge(clk);
 accumulator<= sum;
 end process;
 output : result<= accumulator;
 
end Behavioral;

 

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Don't use std_logic_unsigned
There are conflicts between numeric_std (the IEEE standard library) and the non-standard synopsys library.

You also need to learn how to use the proper VHDL data types.

a,b : in std_logic_vector (7 downto 0);

a and b are both std_logic_vector.

signal i : std_logic_vector(2 downto 0);
a_mux : ai <= a( std_logic_vector (i));////error here
b_mux : bi <= b( std_logic_vector (i)); /// error here

i is defined as a std_logic_vector, but indices have to be integer values, hence a(1), a(3) are okay, but a("000") is not okay.

Cast i to integer to use it as an index or better yet define it as unsigned (integer).

I think you need to read a VHDL book.

 

[prashanthi999]

thanku for replying ,sir if we dont use "std_logic_unsigned", its showing u cant use all the arithmetic operations,
secondly do u mean it like this

ai <= a( to_integer (i)); 
bi <= b( to_integer (i));

 

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thanku for replying ,sir if we dont use "std_logic_unsigned", its showing u cant use all the arithmetic operations,

Because you aren't supposed to use arithmetic on std_logic_vector.
std_logic_vector is meant to be a container for a bunch of bits, not a number. If you want to use something as a number use unsigned, signed, integer, etc. Then you can use arithmetic operations.
Before the IEEE actually "fixed" VHDL there wasn't any types that could be used with arithmetic operations. Synopsys wrote their own library to allow std_logic_vector to be used for arithmetic operations. They then went and did something ridiculous and stuck it in the IEEE library (against IEEE's intentions for the IEEE library). They should have made a SYNOPSYS library and stuck their stuff in there, if they had we wouldn't be stuck with everyone thinking that IEEE.std_logic_unsigned etc. are official IEEE libraries. They aren't and never have been!

Like I said you need to read a VHDL book e.g. Pedroni, Circuit Design and Simulation with VHDL.

ai <= a( to_integer (i)); 
bi <= b( to_integer (i));

sure go ahead and do that...
You'll just look like you're a VHDL dinosaur and haven't evolved enough to walk upright. ;-)

FYI, The IEEE added numeric_std in something like 1995 so it's been around for nearly 20 years!

 

[TrickyDicky]

sure go ahead and do that...
You'll just look like you're a VHDL dinosaur and haven't evolved enough to walk upright. ;-)

FYI, The IEEE added numeric_std in something like 1995 so it's been around for nearly 20 years!

It was added to the 1993 revision of the language.
The big problem was vendors didnt really support it for years (MAX plus 2 was still around in 2000+, and had terrible VHDL support) so the old textbooks still linger.

TO the OP: I highly suggest you find a decent VHDL tutorial.

 

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It was added to the 1993 revision of the language.
The big problem was vendors didnt really support it for years (MAX plus 2 was still around in 2000+, and had terrible VHDL support) so the old textbooks still linger.

what do you expect when the tool is free? Paid for tools develop support much faster than those free or vendor subsidized tools.

TO the OP: I highly suggest you find a decent VHDL tutorial.

A decent online tutorial? Good luck with that. ;-)