Array for values of a function

[ctzof]

I want to create an array in Verilog which is going to contain the values x,y of a given function (not a known one just a line calculated from values). So each content of the array is going to contain a value of x and a value of y. So lets say that I have the following values for (x,y)

3,2 5,10 1,5

The final array will look something like this

Table[x][y]

Table[0][3][2]
Table[1][5][10]
Table[3][1][5]
Is it possible to make this array in verilog and be synthesizable. If yes how we can access each point on this array?

Thanks

 

[sreevenkjan]

you can check the following links to create a 2D array.

https://vhdlguru.blogspot.de/2010/02/arrays-and-records-in-vhdl.html

https://www.alteraforum.com/forum/showthread.php?t=31305

I guess you can find your answers.

 

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I want to create an array in Verilog which is going to contain the values x,y of a given function (not a known one just a line calculated from values). So each content of the array is going to contain a value of x and a value of y. So lets say that I have the following values for (x,y)

3,2 5,10 1,5

The final array will look something like this

Table[x][y]

Table[0][3][2]
Table[1][5][10]
Table[3][1][5]
Is it possible to make this array in verilog and be synthesizable. If yes how we can access each point on this array?

Thanks

you can check the following links to create a 2D array.

https://vhdlguru.blogspot.de/2010/02/arrays-and-records-in-vhdl.html

https://www.alteraforum.com/forum/showthread.php?t=31305

I guess you can find your answers.

Both of your answers are for VHDL! The OP asked for Verilog.

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Code Verilog - [expand]
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reg [15:0] my_array [0:7] [0:31];
my_array[29][5][15:0]

---

I may have the 1st (29) and the 2nd (5) swapped, so you should probably create a testcase to verify which index comes first. Note the order of the indices stays the same regardless how many dimensions the array has. I'm not sure if synthesis tools support more than two dimensions on the right side (I've never needed to try).

 

[ctzof]

Both of your answers are for VHDL! The OP asked for Verilog.

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Code Verilog - [expand]
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reg [15:0] my_array [0:7] [0:31];
my_array[29][5][15:0]

---

I may have the 1st (29) and the 2nd (5) swapped, so you should probably create a testcase to verify which index comes first. Note the order of the indices stays the same regardless how many dimensions the array has. I'm not sure if synthesis tools support more than two dimensions on the right side (I've never needed to try).

Thanks for the answer. I've made a simple code based on this approach and it compiles just fine without errors. The problem is that it doesn't synthesize any circuit. Here is the code

module memc2 (outp1, outp2, outp3, outp4);
    output[2:0] outp1, outp2, outp3, outp4;
 
    reg [2:0] mem [1:0][1:0];

  initial begin 
    mem[0][0][2:0]=6'b000000; 
    mem[0][1][2:0]=6'b001001; 
    mem[1][0][2:0]=6'b010010;
    mem[1][1][2:0]=6'b011011;

  end



  assign outp1 = mem[0][0][2:0];
  assign outp2 = mem[0][1][2:0];
  assign outp3 = mem[1][0][2:0];
  assign outp4 = mem[1][1][2:0];

endmodule

 

[TrickyDicky]

What do you expect, it just synthesises to a loaf of constants, so there is no circuit there.

 

[ctzof]

Can you help me with the above code. I want to compare an input with x values of this array. If the value is greater than a specific x I want to save the index of this x and perform an addition with y pair. The result goes to the output. The code compiles just fine but again its not synthesizes any circuit. The idea later is to use this array to perform linear interpolation and determinate the value of y for a given value of x that its not inside the array. The code is the following. I save the save value for x and y for each index.

module memc2 (inp,outp);
    input[2:0] inp; 
    output[2:0] outp; 
    reg index1;
    reg index2;
    reg index3;
    reg index4;
    reg [2:0] mem [1:0][1:0]; //2d array that contains the values of x and y there are two points each of them has a value of x and y of 3bits

  initial begin 
    mem[0][0][2:0]=3'b001; //x1
    mem[0][1][2:0]=3'b001; //y1
    mem[1][0][2:0]=3'b010; //x2
    mem[1][1][2:0]=3'b010; //y2

  end

  always @(*) 
  begin 
    if (inp < mem[0][0][2:0] )//compare with x0
    begin
      index1 =0;
      index2=0;
      index3 =0;
      index4=1;
    end 
    else if(inp < mem[1][0][2:0] )//compare with x1
    begin 
      index1 =0;
      index2=1;
      index3 =1;
      index4=1;
      end 

  end 

  assign outp = mem[index2][index1][2:0] + mem[index4][index3][2:0]; 
endmodule

 

[ctzof]

This is a simplified version of the code. I use 1 dim array with 6 bit. I use the first three bits to store the value of x and the other three to store the value of y. The code still compiles but the thing is that I don't get also any synthesized circuit. I assume that there is a problem with accessing the values of the array.

module memc (inp,outp,clk,reset);
    input[2:0] inp;
    input clk, reset; 
    output[2:0] outp;
    reg[2:0] outp;
    wire [2:0] test;
    reg [5:0] mem[2:0];

initial
begin 
    mem[0] <= {3'b000, 3'b000};//y0,x0
    mem[1] <= {3'b001, 3'b001};//y1,x1
    mem[2] <= {3'b010, 3'b010};//y2,x2
end


assign test ={inp<mem[0][2:0],inp<mem[1][2:0],inp<mem[2][2:0]}; //create a test vector by comparing inp with xo,x1,x2
always @(test)
case (test)
3'b1xx: outp=mem[0][2:0]+mem[0][5:3];//if 0<inp<x1
3'b0xx: outp=mem[1][2:0]+mem[1][5:3];//if x1<inp<x2
3'b00x: outp=mem[2][2:0]+mem[2][5:3];//if x2<inp<x3
default: outp=3'b00;
endcase
endmodule

 

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Initial does not work as there is nothing driving the mem array.

The following modified code produces the following schematic (which has latches)
code:

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Code Verilog - [expand]
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module memc2 (inp,outp);
    input[2:0] inp; 
    output[2:0] outp; 
    reg index1;
    reg index2;
    reg index3;
    reg index4;
    wire [2:0] mem [1:0][1:0]; //2d array that contains the values of x and y there are two points each of them has a value of x and y of 3bits
 
  assign  mem[0][0][2:0]=3'b001; //x1
  assign  mem[0][1][2:0]=3'b001; //y1
  assign  mem[1][0][2:0]=3'b010; //x2
  assign  mem[1][1][2:0]=3'b010; //y2
 
 
  always @(*) 
  begin 
    if (inp < mem[0][0][2:0] )//compare with x0
    begin
      index1 =0;
      index2=0;
      index3 =0;
      index4=1;
    end 
    else if(inp < mem[1][0][2:0] )//compare with x1
    begin 
      index1 =0;
      index2=1;
      index3 =1;
      index4=1;
      end 
 
  end 
 
  assign outp = mem[index2][index1][2:0] + mem[index4][index3][2:0]; 
endmodule

---

schematic of above code:

You should fix the code (this is the danger of combinational logic, when done incorrectly) and add an else clause.