Array 1D in VHDL Please

[azwaa]

Hi everybody !

I want to add(xor) data with CD in shape array and the result would be S

Can you help me correcting this code :

library ieee;use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity cdm is 


port (
         clk : in std_logic ;
         rst : in std_logic  ;
         data: in std_logic  ;
        odata: out std_logic  ;
         CD  : in  std_logic_vector(15 downto 0) ;
        isis :out  integer range 0 to 3  ;
         S   :out std_logic_vector(3 downto 0 ));
end entity ;


architecture beh of cdm is 
    type tab is array(3 downto 0)of std_logic_vector(15 downto 0);
        
        signal i      :integer range 0 to 3 ;
        signal idata  :std_logic  ;
        signal itab :tab ;
        begin 
         code :process(clk,rst)
               begin 
                    if(rst='1')then 
                     itab(i)<="0000" ;
                    else 
                        if(clk'event and clk='1')then 
                          
                           itab(i)<= not(CD(15 downto 12)xor (data));
                           S(i)<=itab(i);
                           i<= i+1 ;
                           
                           itab(i)<=not(CD (11 downto 8) xor(data));
                            S(i)<=itab(i);
                            i<=i+1 ;
                            
                           itab(i)<=not( CD(7 downto 4) xor (data));
                            S(i)<=itab(i);
                            i<=i+1;
                            
                           itab(i)<=not( CD(3 downto 0) xor (data));
                            S(i)<=itab(i);
                            i<=i+1 ;
                           
                           
                           
                                   
                           if i=3 then 
                                 idata<=data ;
                            end if ;
                          end if ;
                       end if ;
                  end process ;
                  isis<=i;
                 
                 odata<=idata ;
   end architecture ;

Thank you in advance for your reponse

- - - Updated - - -

Hi !

In fact; I shall want to make BPSK Modulation

- - - Updated - - -

Hi !

In fact; I shall want to make BPSK Modulation

 

[TrickyDicky]

You already had a response on the altera forums here:
https://www.alteraforum.com/forum/showthread.php?t=45040

 

[FvM]

You can't xor std_logic with a std_locgic_vector. Please consider which logical operation is exactly intended.

I noticed that you posted the same erroneous code at Altera Forum. Forum members suggested corrections that have been said to work correctly. Why don't you proceed from this point?

 

[azwaa]

Thank you My friends !

In fact ; I have another problem :

"Error (10500): VHDL syntax error at cdma_testbipo.vhd(12) near text "type"; expecting an identifier ("type" is a reserved keyword), or "constant", or "file", or "signal", or "variable" ""

can you help me plz :

---

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity cdma_testbipo is 
 
port (
         clk : in std_logic ;
         rst : in std_logic  ;
         data: in std_logic  ;
        odata: out std_logic  ;
        type Re is array(0 to 3)of integer range 0 to 15;
           signal CD: Re ;
        isis :out  integer range 0 to 3  ;
         S   :out integer range -8 to 7 );
end entity ;
 
architecture beh of cdma_testbipo is 
    
    type RAM is array (0 to 3) of integer range -8 to 7;
        signal i      :integer range 0 to 3 ;
        signal code   : RAM;
        signal idata  :std_logic  ;
        
        begin 
   
        code(0)<=CD(15 downto 12);
        code(1)<=CD(11 downto 8) ;
        code(2)<=CD(7 downto 4) ;
        code(3)<=CD(3 downto 0) ;
         bpsk :process(clk,rst)
               begin 
                    if(rst='1')then 
                        i<= 0;
                    else 
                        if(clk'event and clk='1')then 
                            
                            i<=i+1 ;
                            if(idata='0') then 
                                s<=-code(i); 
                            else  
                                s<=code(i);
                            end if;
                
                            if(i=3) then 
                                idata<=data;
                            end if;
                              
                          end if ;
                      end if ;
                  end process ;
                  isis<=i;
                 
                 odata<=idata ;
   end architecture ;

---

Thank you

 

[ads-ee]

you can't declare a type or a signal in the middle of the entity port declaration.

move the lines:

type Re is array(0 to 3)of integer range 0 to 15;
signal CD: Re ;

to below the architecture statement.


Regards

 

[azwaa]

Yeah ;

it's done !

but problem always return !!

""""

Error (10381): VHDL Type Mismatch error at cdma_testbipo.vhd(27): indexed name returns a value whose type does not match "integer", the type of the target expression"""""""

so we should to convert CD in array !!

Thank you

- - - Updated - - -

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cdma_testbipo is 

port (
         clk : in std_logic ;
         rst : in std_logic  ;
         data: in std_logic  ;
        odata: out std_logic  ;
        isis :out  integer range 0 to 3  ;
         S   :out integer range -8 to 7	);
end entity ;

architecture beh of cdma_testbipo is 
    
     type Re is array(0 to 3)of integer range 0 to 15;
           signal CD: Re ;
    type RAM is array (0 to 3) of integer range -8 to 7;
        signal i      :integer range 0 to 3 ;
        signal code   : RAM;
        signal idata  :std_logic  ;
        
        begin 
   
		code(0)<=CD(15 downto 12);
		code(1)<=CD(11 downto 8) ;
		code(2)<=CD(7 downto 4) ;
		code(3)<=CD(3 downto 0) ;
         bpsk :process(clk,rst)
               begin 
                    if(rst='1')then 
                        i<= 0;
                    else 
                        if(clk'event and clk='1')then 
                            
                            i<=i+1 ;
                            if(idata='0') then 
								s<=-code(i); 
							else  
								s<=code(i);
							end if;
				
							if(i=3) then 
								idata<=data;
							end if;
                              
                          end if ;
                      end if ;
                  end process ;
                  isis<=i;
                 
                 odata<=idata ;
   end architecture ;

 

[FvM]

At first sight, changing the data to integer and integer arrays has brought up more confusion rather than fixing the original problem. Still not clear what you want to achieve.

code(0)<=CD(15 downto 12);

Please notice that the compiler just stops at the first error, detecting that LHS is an integer but RHS an integer array, so it can't be assigned. Next would be to detect that the array range doesn't exist and has wrong direction, CD has a range 0 to 3. Finally the integer ranges don't fit.