ARM9 interrupt handler code

[bejoy]

ARM9 int handler

		.global  	entrypoint
		.sect	 ".handlers"
		.global	Reset_Handler,Undefined_Handler,SWI_Handler,Prefetch_Handler
		.global	Abort_Handler,IRQ_Handler,FIQ_Handler


entrypoint:

Reset_Handler:
		B	Reset_Handler1

Undefined_Handler:
        		B       	Undefined_Handler

SWI_Handler:
        		B      	 SWI_Handler 

Prefetch_Handler:
        		B      	 Prefetch_Handler

Abort_Handler:
        		B      	 Abort_Handler

		NOP 
IRQ_Handler:
       		B       	IRQ_Handler	

FIQ_Handler:
        		B      	 FIQ_Handler




Mode_USR		.set	0x10
Mode_FIQ		.set	0x11
Mode_IRQ		.set	0x12
Mode_SVC		.set	0x13
Mode_ABT		.set	0x17
Mode_UND		.set	0x1B
Mode_SYS		.set	0x1F 		; available on ARM Arch 4 and later

I_Bit			.set	0x80	/?	;when I bit is set, IRQ is disabled
F_Bit			.set	0x40	/?	;when F bit is set, FIQ is disabled




Len_FIQ_Stack                	.set	512   
Len_IRQ_Stack               	.set           512 
Len_ABT_Stack                	.set           512   
Len_UND_Stack                	.set           256   
Len_SVC_Stack                	.set         1024
Len_USR_Stack                	.set         1024



Offset_FIQ_Stack                     .set	0                               
Offset_IRQ_Stack                     .set          Offset_FIQ_Stack + Len_FIQ_Stack
Offset_ABT_Stack                    .set           Offset_IRQ_Stack + Len_IRQ_Stack
Offset_UND_Stack                    .set          Offset_ABT_Stack + Len_ABT_Stack
Offset_SVC_Stack                    .set          Offset_UND_Stack + Len_UND_Stack
Offset_USR_Stack                    .set          Offset_SVC_Stack + Len_SVC_Stack




	
Reset_Handler1:

		
		LDR     r0, stack_s	//r1		


		MSR     CPSR_c, #Mode_FIQ | I_Bit | F_Bit 	; No interrupts
		SUB     sp, r0, #Offset_FIQ_Stack
		
		MSR     CPSR_c, #Mode_IRQ | I_Bit | F_Bit 	; No interrupts
		SUB     sp, r0, #Offset_IRQ_Stack

		MSR     CPSR_c, #Mode_ABT | I_Bit | F_Bit 	; No interrupts
		SUB     sp, r0, #Offset_ABT_Stack

		MSR     CPSR_c, #Mode_UND | I_Bit | F_Bit 	; No interrupts
		SUB     sp, r0, #Offset_UND_Stack

		MSR     CPSR_c, #Mode_SVC |  F_Bit 		; No interrupts	I_Bit |
		SUB     sp, r0, #Offset_SVC_Stack



		LDR		R0,op1_s
		LDR		R1,[R0]


loop:	B	loop


stack_s		.word	 top_of_stack
op1_s		.word	op1


        	.sect  ".stack"

top_of_stack:


			.sect ".math_memory"

op1		.word	0x12345678
op2		.word	0x23456789
res		.word	0x00000000[color=red][/color]

 

[amraldo]

What is your question?
--
Amr

 

[bejoy]

can u pls give me an idea on the address range that i can branch to from this function.
while linking in certain range i got an error that it exceeds 24 bit value

 

[amraldo]

Send the complete log please.
--
Amr

 

[bejoy]

i shall send the detailed error 2orrow.
it was saying that u cant branch to a location whose address exeeds from present by 24 bits.
when i wrote that piece of code in main it was cleared.
i would like to know is there any alternative way to handle such situations

 

[amraldo]

I have 2 c the code and know your compiler.
--
Amr

 

[bejoy]

its code composer studio

there z no error in the code.

i occurs when we call a function which we have maped to certain location in the linker command file.
the location in the linker file creates the problem.

i read in the user guide about some 24 bits are used for address calculaion.

i wud like to know any alternative other than changing the mapped address in linker

 

[amraldo]

The 24-bit offset is a hardware limitation of the Branch instruction. It is a rule forced by the ARM architecture itself.

Why this function has to be in that certain location?

--
Amr

 

[bejoy]

ok i just want to know is there any tricks ....

Added after 16 seconds:

thank you

 

[amraldo]

You can do a self modifying code that branches to a certain location and at this location , there is a a function that can load any address to PC.
--
Amr