matrixofdynamism
Advanced Member level 2
Often, we may want to carry out arithmatic in our FPGA design which means that this shall be implemented in the RTL. Under such circumstances, is it a good idea to merely write C=A+B, C=A-B in the RTL or does one create an adder of the correct size in RTL, instantiate it and then use that instance to carry out the aritmatic? My question also applies to multiplication. The only difference with multiplication is that we now have hard DSP blocks in the FPGAs thus writing A*B can be directly synthesized. Assume that we are talking about standard logic vectors which represent fixed point arithmatic.
Also, is it that division is only rarely carried out in digital circuits? I mean, if we write A+B, A-B or A*B, the synthesisi tool (lets say Altera Quartus) can synthesize circuit to do this. What would synthesis tools do with division operator? After all, it can lead to fractional results and irrational numbers too.
Also, is it that division is only rarely carried out in digital circuits? I mean, if we write A+B, A-B or A*B, the synthesisi tool (lets say Altera Quartus) can synthesize circuit to do this. What would synthesis tools do with division operator? After all, it can lead to fractional results and irrational numbers too.