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Are variables in VHDL are synthesizable or not?

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kunal1514

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Hi All,

Can any body tell that whether variables in VHDL are synthesizable or not
 

Variables

Technically, variables are synthesizable.
However, synthesis results of variables is somewhat tool dependent and is not recommended for production designs.
 

Re: Variables

kunal1514 said:
Hi All,

Can any body tell that whether variables in VHDL are synthesizable or not

I've used them successfully in the past, there are some guidelines on their usage - write before you read etc. A good design checker such as Leda (www.synopsys.com) or SpyGlass would help there.

HTH
Ajeetha, CVC
www.noveldv.com
 

Re: Variables

Yes, Variables are very much synthesizable and I have also used them in couple of my designs. what needs to be understood is the differences between Signals & Variables and how exactly they behave.

Regards.
 

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