Are Texas chips more susceptible to ESD damage?

[cupoftea]

Why is it that all ti.com chips have the warning as on pg 39 of the UCC28070A datasheet....

UCC28070A

https://www.ti.com/lit/ds/symlink/ucc28070a.pdf?ts=1661031383070&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FUCC28070A

"These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates."

Other chips rarely have such a warning. Are ti.com chips more susceptible to ESD?...or are ti.com just more into their ESD protection measures?
They state the HBM and CDM, so why tell the world that their chips have "limited built-in ESD protection" ?

 

[dick_freebird]

Actual ESD worst case handling withstand may or may not differ.

What differs is that TI is a mature (to say the least) semiconductor company that recognizes the value of telling customers how not to create field returns in quantity. Any one that listens, has saved the company money (in avoided failure analysis) and improved their own manufacturing quality, and one less black eye over an avoidable problem.

 

[BigBoss]

All ESD Protections are limited. It's just a warning.
There are standards for ESD handlings and they warn you to protect the IC.

 

[FvM]

Not all manufacturers include the ESD rating in standard datasheets. Some have production handling specs, e.g. also MSL (moisture sensitivity level) in separate documents.

 

[crutschow]

It would be impossible to provide "unlimited" built-in ESD protection so, by definition, all ESD protection is "limited".

 

[cupoftea]

Thanks, i must admit i believe that the smaller package chips, like TSSOP and MSOP etc, are more susceptible to ESD damage than the larger SO and SOICs, generally speaking.
Also, believe that BiCMOS is generally more robust than CMOS.
I wonder though sometimes?

 

[dick_freebird]

I would not generalize across technologies because in
the end ESD protection is more about design choices
(such as whether to place even one ESD diode on a
pin, if it impacts die area, which it must).

I do believe that bipolar devices are, at the low end,
more rugged than a MOS gate in the sense of
catastophic unrecoverable failure, but bipolars can
still easily get drifted enough to fail spec at low
voltages (really, the avalanche time*current profile)
and fixing that on a coarse geometry, high common
mode voltage range pin is all kinds of funsies (if
it'll fit, and work, which is part negotiation and part
"Fun Surprize Pak!".