Are Functions in Verilog synthesizable?

[kunal1514]

Functions

Can any body tell me whether "Functions" in verilog are synthesizable or not if yes provide me some relevant proof. it's urgent.

 

[atmaca]

Re: Functions

it depends on the compiler u use

 

[beta0]

Functions

Sometimes we use the "Function" to emplmention combinational circuit.

 

[aji_vlsi]

Re: Functions

Can any body tell me whether "Functions" in verilog are synthesizable or not if yes provide me some relevant proof. it's urgent.

Functions when used in RTL context (meaning no use of $time etc) are fully synthesisable. WHat "proof" do you need? For whom? Refer to IEEE 1364.1 standard if needed. Or use your synthesis tool as a proof.

HTH
Ajeetha, CVC
www.noveldv.com