Are Casex and Casez synthesizable ?

[spartanthewarrior]

Can any body tell me that whether "Casex" or "Casez" are synthesizable or not.

 

[kishore2k4]

case vs casex

They are but lookout for inferred latches, or just full_case directive.

 

[spauls]

casez vs casex

casez is synthesizable but casex is not.

 

[Adam.Yakuvitz]

casex synthesis

Hmm,
The statement

casez is synthesizable but casex is not.

is not true. Both casex and casez are synthesizable. Casex generates a don't-care space for unspecified state points. Casez uses a "Z logic value" to represent a don't-care bits.

 

[spartanthewarrior]

casex vs casez

Here u got traped buddy,

As u said that Casex and Casez are synthesizable but i hope as we know "x" and "z" are not synthesizable. So will it be possible that Casex and Casez are synthesizable.

Spartan

 

[Adam.Yakuvitz]

casez

Ahhh, the "X" condition debate.

There are two meanings to an "X". For a simulation, "X" means dont-know but for a synthesis "X" means a don't care. X is synthesizable because it could be anything. All X means it is 1 or a 0.

The statement of a "Z" not being synthesizable is also incorrect. What do you think this verilog code reveals . .
tri [0:3] buf_out = en? in: 4'bz;

Ta-Da! A 4-bit tri-state bus that goes "Z" when disabled.

--
ay

 

[spartanthewarrior]

casex and casez

Hi Again,

Just explain me that How does the Synthesis tool came to know that i have to put

"1" or "0" in place of "x" or "z" for exampel

Case (Byte)

4'b001x : a <= 4'b0000;
4'b00x0 : a <= 4'b0001;
endcase

Then how does synthesis tool came to know that i have to put "1" or "0' in place of "x".