architecture for 4 bit ripple couner using structural model.

[Ayyappa Gollu]

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Code VHDL - [expand]
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/////////////////////////////////////////////////////////////
structural code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ripple_counter_4bit is
    Port ( count : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           a : out  STD_LOGIC_vector(o to 3));
end ripple_counter_4bit;
 
architecture Behavioral of ripple_counter_4bit is
component dff port(d_in,clock,reset:in std_logic;
                         d_out:out std_logic);
                         end component;
 begin
d1:dff port map(~a(0),count,reset,a(0));
d2:dff port map(~a(1),a(0),reset,a(1));
d3:dff port map(~a(2),a(1),reset,a(2));
d4:dff port map(~a(3),a(2),reset,a(3));//this is line 44.
end Behavioral;
/////////////////////////////////////////////////////////////////////////////////////

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ERROR:HDLParsers:1411 - "C:/Xilinx92i/ripcount_4/ripple_counter_4bit.vhd" Line 44. Parameter a of mode out can not be associated with a formal port of mode in.

Process "Check Syntax" failed.

 

[barry]

Is there a question here somewhere, or are just throwing code up here for our entertainment?

Also, you post the error, which occurs at line 44, and don't post the code from line 44.

 

[ads-ee]

Also, you post the error, which occurs at line 44, and don't post the code from line 44.

The OP marked the line in the code with //this is line 44.

Though the use of // is not a VHDL comment but a Verilog comment, I don't think this is the code they compiled.

Regarding the error, a port of out cannot be read inside the architecture. I'm kind of surprised you didn't get an error on the d1 instance. You need to make an intermediate signal to allow it to be read, then assign that signal to the output a.

- - - Updated - - -

Forgot to mention if the tool supports 2008 you might get lucky and it supports reading out ports.

 

[TrickyDicky]

This code is really suspect, and clearly not what the OP compiled:

- a is declared with o (letter o) to 3
- use if ~ (which is verilog not command) and the use of it in a port map (illegal in VHDL, even if they used the correct not function)
- All DFF instantiations would give this error, as the output a is connected to all of the d_in ports.

 

[Ayyappa Gollu]

first of all this is not for entertainment and i got this error while checking syntax with xilinx.i'm happy to inform you that i came to know about my errors which were,
1.for signal a both mode and type were wrong in my code.i had typed aut std_logic_vector(o to 3) which should be like a:inout std_logic_vector(0 to 3)--where i had written 'o' instead of '0' and "out" instead of "inout".
2.replaced '~' with 'not' keyword
3.coming to error i had written // instead of -- as comment line to let you know that error is with that particular statement.i didn't compile with that anyway.
4.with these corrections "check syntax" had shown green go but during behavioral simulation got this error

 

[FvM]

1.for signal a both mode and type were wrong in my code.i had typed aut std_logic_vector(o to 3) which should be like a:inout std_logic_vector(0 to 3)--where i had written 'o' instead of '0' and "out" instead of "inout".

Using inout type for a pure output port. Instead of fixing the code by trial and error method, you should probably review your favourite VHDL book for the suggested way.

Unless your dff component has a falling edge sensitive clock input, the ripple counter won't work correctly.