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APB protocol testing

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av24

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please find the error though I have coded testbench and output wasn't displaying:

Code:
// Code your design here
module apbslave(
  input pclk,
  input prstn,
  input [31:0] pwdata,
  input [7:0] paddr,
  input psel,
  input penable,
  input pwrite,
  output reg [31:0] prdata
);


  reg [31:0] mem [0:255];

  reg [1:0] state;
  reg [1:0] idle;
  reg [1:0] setup;
  reg [1:0] write;
  reg [1:0] read;

  always @(posedge pclk or negedge prstn)
    begin
      if(!prstn) begin
        prdata <= 0;
      end else begin
        case(state)
          idle : begin
            prdata <= 0;
            state <= setup;
          end
          setup : begin
            prdata <= 0;
            if(psel & !penable) begin
              if(pwrite) begin
                state <= write;
              end else begin
                state <= read;
              end
            end
          end
          write : begin
            if(psel & penable & pwrite) begin
              mem[paddr] <= pwdata;
            end
            state <= setup;
          end
          read : begin
            if(psel & penable & !pwrite) begin
              prdata <= mem[paddr];
            end
            state <= setup;
          end
        endcase
      end
    end
endmodule

testbench:
module tb();
reg pclk;
reg prstn;
reg [31:0] pwdata;
reg [7:0] paddr;
reg psel;
reg penable;
reg pwrite;
wire [31:0] prdata;

apbslave P(pclk,prstn,pwdata,paddr,psel,penable,pwrite,prdata);


always #5 pclk = ~pclk;

initial begin
prstn = 0;
pclk = 0;
penable = 0;
psel = 0;
pwrite = 0;
end

initial begin
$dumpfile("dump.vcd");
$dumpvars(0,tb);

#2 prstn = 1;
#6 psel = 1;
#2 penable = 1;

#5 pwrite = 1;
#5 pwdata = $random;
#5 paddr = $random;
#5 pwrite = 0;
#2 prstn = 0;
#200 $finish;
end
endmodule
 
Last edited:

The forum members here are real human beings and not compilers. Please ask a structured and detailed question providing all relevant information, if you want to get help.
 

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