Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
A fifo is a memory + control logic surrounding it, lets take an example for this:
Consider a case for holding badminton shuttlecocks , now one by one start putting in the shuttle cocks from the bottom of the case , lets assume that a total of 10 shuttle cocks only got fit into the case. Now this is termed as max_occupancy of this (fifo) shuttlecock case. The moment you push another one , the first one that you pushed would come out . this is termed as an over flow of (fifo) shuttlcock holder.
Now, Lets say you pushed only a single shuttle cock into the empty case and you want to play using that shuttle cock , now the occupancy of the fifo is 1 and when you take the shuttle out of the box , its also called as a "fifo read".
The procedure of placing the shuttlecock into the case is called as "fifo write ".
Hope you can relate this to yr design.
Fifo designs are not easy (if you want to do them correctly) ; there are problems which verification also wouldnt be able to trace. Its due to the common mode errors. Both people think that whatever they are doing is correct while both are wrong.
There s another aspect to fifo design if the writes and reads donot belong to the same clock domain. In such cases , you would need to bring the write clock synchronised to the read clock.
I think using dual port Ram will solve a lot of the FIFO implementation problems.
Xilinx have an app note regarding implementing FIFO using the Vertix 2 dual port RAM
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
