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any tool from VHDl to verilog

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google XHDL3 sw but it has some code size restrictions if its a demo version.
 

Not only some but it had a lot of restrictions when you higher the level
 

Why do you want to convert VHDL to Verilog. If you had written any part of code in VHDL try to use PLI to get better performance.
 

Sure you can use PLI which will be comfortable than going for other stuffs
 

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