Any Simple method to test Function in Verilog

[choonlle]

Test the function in Verilog can be boring if u try to run simulation and see the output. Do you think any method can be faster to rest function whether correct or not>

 

[dragonight_x]

Well, you can always write a test bench for your function, it’s easy and fast . Or you can do it the old fashion way but by making a macro instead of making it step by step.