Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Any nice idea for MSc thesis/Project?

Status
Not open for further replies.

wassa

Junior Member level 3
Joined
Dec 2, 2003
Messages
27
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
168
asic projects for thesis

I need some nice idea for my MSc thesis/project. My areas of interst are embedded and ASIC. It would be nice if some helping material is provided for.
 

aji_vlsi

Advanced Member level 2
Joined
Sep 10, 2004
Messages
646
Helped
85
Reputation
170
Reaction score
12
Trophy points
1,298
Location
Bangalore, India
Activity points
4,946
how big is an msc thesis

wassa said:
I need some nice idea for my MSc thesis/project. My areas of interst are embedded and ASIC. It would be nice if some helping material is provided for.
Hi,
What about building a SoC for say image prcoessing or signal processing applications from available open cores? My company can help you with guidance (note: we will NOT do the coding for you) if needed and if our timelines permit. Write to me if interested @ ajeetha <> gmail.com. But please do your homework before that - this SoC will be a model/dummy and not necessarily a commercial strenght. We may even say that it will be a Transaction level model and not synthesizable. All work will be in "front end" no back end.

Regards
Ajeetha, CVC
www.noveldv.com
 
  • Like
Reactions: neenu

    neenu

    Points: 2
    Helpful Answer Positive Rating

newcpu

Member level 4
Joined
Oct 30, 2005
Messages
77
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,286
Activity points
1,818
msc project thesis topic forum

What's about ASIC challenges for 90nm and 65nm? Modern ASIC is shifting to 90nm and 65nm. And there are some challenging problems waiting to be conquered.
 

its_thepip

Member level 2
Joined
Sep 15, 2006
Messages
44
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,288
Activity points
1,513
ajeetha @gmail.com

ASIC has started getting down from 65nm to 45nm now-a-days...
So how about implementing our conventional digital...analog circuits in this technology......like say some fabrication types/////
Else , see these links to get more info....
1) University of California, Berkeley
2)MIT
3)www.project.org
4)www.sonsiviri.com
5) Our very own edaboard diwcussion forum has loads of ideas....
\]
 

wwfhm2002

Member level 5
Joined
Dec 7, 2003
Messages
83
Helped
6
Reputation
12
Reaction score
5
Trophy points
1,288
Activity points
686
digital msc theses topics

I think chip production test is a very good topic as test cost is a big part of whole chip. such as a 4x4mm chip, the test cost may be 1/3 of whole chip, while others is die and package.
 

PLLADCDAC

Newbie level 4
Joined
Oct 12, 2006
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,304
nice project ideas forums

I think low power should be a good idea at this level
 

ray123

Member level 3
Joined
Nov 25, 2003
Messages
60
Helped
6
Reputation
12
Reaction score
3
Trophy points
1,288
Activity points
327
you need to discuss it with your adviser.
I doubt you can do whatever project you want.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top