Any material discussing the process variation of cmos

[OMEsystem]

local device mismatch cmos

Plaease suggest the materials which discusses the process variation and design
for mass production in cmos technology, especially in deep sub-micron scale.
Any realated topics is welcome.

Thanks,

 

[sankudey]

cmos local versus process mismatch

Hi...a theoritical discussion is there in almost every analog design books....some of the followings may be help ful...

Books:

1. Razavi....Analog Design (CMOS)

2. Gray-Meyer: Four Author-->Analog Design

3. Johns-Martin: Analog Design:

4. Baker : CMOS

Some Paers:

1. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 3, MARCH 2003: Understanding MOSFET Mismatch for Analog Design: Patrick G. Drennan, Member, IEEE, and Colin C. McAndrew, Senior Member, IEEE

2. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 6, JUNE 2005; Device Mismatch and Tradeoffs in the Design of Analog Circuits; Peter R. Kinget, Senior Member, IEEE

3. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 8, AUGUST 2005; A Compact Model of MOSFET Mismatch for Circuit Design; Carlos Galup-Montoro, Member, IEEE, Márcio C. Schneider, Member, IEEE, et al;

4. IEEEJOURNAL OF SOLID-STATECIRCUITS,VOL. SC-21,NO. 6,DECEMBER 1986; Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design; KADABA R. LAKSHMIKUMAR, MEMBER, IEEE, ROBERT A. HADAWAY, AND MILES A. COPELAND, SENIOR MEMBER, IEEE

5. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 21, NO. 2. FEBRUARY 1992; Statistical Modeling of Device Mismatch MOS Integrated Circuits; Christopher Michael and Mohammed Ismail, Senior Member, IEEE

6. Impact of transistor mismatch on the speed-accuracy-power trade-off of
analog CMOS circuits
Peter Kinget and Michiel Steyaert
Katholieke Universiteit Leuven, ESAT-MICAS
Kard. Mercierlaan 94, B-3001 Heverlee, Belgium

7. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 46, NO. 7, JULY 1999 937
Transactions Briefs
Analytical Expressions for Harmonic Distortion
at Low Frequencies due to Device Mismatch
in CMOS Current Mirrors
Erik Bruun

You also could refer to some layout books....like following



All the books are availbe in this board. Most of the papers so....search them....if you don't find let me know....

Hope would help...

sankudey

 

[OMEsystem]

pvt variations in cmos chip solid state circuits

Thanks for your reply, would you recommend the paper dedicating on
the process variation of sub-micron cmos and its yied improvement by design?

Thanks,

 

[sankudey]

mismatch mos devices with temperature

Hey,
The above papers and particularly the book is suitable for this....some others are given below...

1.Robust design of low power CMOS analogue integrated circuits
Tarim, T.B.; Ismail, M.;
Circuits, Devices and Systems, IEE Proceedings [see also IEE Proceedings G- Circuits, Devices and Systems]
Volume 148, Issue 4, Aug. 2001 Page(s):197 - 204
Digital Object Identifier 10.1049/ip-cds:20010340

Summary: As feature sizes move into the deep submicron ranges and power supply voltages are reduced, the effect of both device mismatch and inter-die process variations on the performance and reliability of analogue integrated circuits is magnified. The stati.....

2. The influence and modeling of process variation and device mismatch for analog/rf circuit design
Yuhua Cheng;
Devices, Circuits and Systems, 2002. Proceedings of the Fourth IEEE International Caracas Conference on
17-19 April 2002 Page(s)046-1 - D046-8
Digital Object Identifier 10.1109/ICCDCS.2002.1004068

Summary: The influence of local process variation and device mismatch to the electrical characteristics of resistors, capacitors, and MOSFETs is reviewed. The discussion is mainly focus on the device mismatch as it becomes more and more important in analog de.....

3. Techniques for On-Chip Process Voltage and Temperature Detection and Compensation
Khan, Q.A.; Siddhartha, G.K.; Tripathi, D.; Wadhwa, S.K.; Misri, K.;
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
03-07 Jan. 2006 Page(s):581 - 586
Digital Object Identifier 10.1109/VLSID.2006.155

Summary: This paper presents techniques to detect process, voltage and temperature (PVT) variations in an integrated circuit chip and wafer. Conventional techniques are limited to detection of Process Variations in which the MOS devices (NMOS and PMOS) move i.....

4. Post silicon power/performance optimization in the presence of process variations using individual well adaptive body biasing (IWABB)
Gregg, J.; Chen, T.W.;
Quality Electronic Design, 2004. Proceedings. 5th International Symposium on
2004 Page(s):453 - 458
Digital Object Identifier 10.1109/ISQED.2004.1283715

Summary: Continued scaling of silicon process technologies beyond the 90nm node will face problems due to within die process variations. The increasing relative magnitude of within die process variations will cause power-frequency distributions to widen, thus.....

5. Optimal body bias selection for leakage improvement and process compensation over different technology generations
Neau, C.; Roy, K.;
Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on
25-27 Aug. 2003 Page(s):116 - 121
Digital Object Identifier 10.1109/LPE.2003.1231846

Summary: We present techniques to determine the optimal body bias (forward or reverse) to minimize leakage current and compensate process variations in scaled CMOS technologies. A circuit trades off sub-threshold leakage with band-to-band tunneling leakage at.....

6. Statistical methods for the estimation of process variation effects on circuit operation
Mutlu, A.A.; Rahman, M.;
Electronics Packaging Manufacturing, IEEE Transactions on [see also Components, Packaging and Manufacturing Technology, Part C: Manufacturing, IEEE Transactions on]
Volume 28, Issue 4, Oct. 2005 Page(s):364 - 375
Digital Object Identifier 10.1109/TEPM.2005.856534

Summary: In this paper, a technology computer-aided design (TCAD) driven method for accurate prediction of the performance spread of integrated circuits due to process variations is presented. The methodology starts with the development of the nominal process.....

HOPE WOULD HELP....
sankudey