One method is to measure capacitance mismatch with a help of additional resistor dac in area where DNL (mismatch) is critical. For binary weighted DAC fiirst at crossing 0111..111 to 1000...000 Then at crossing 001111... 111 to 0111...111
and so on for the first 4-6 bits... Results shoud be stored into a RAM and in normal operation they should be appplied to resistor DAC to cancel mismatch error.
This takes lot of time, and requires additional hardware.
Which resolution do you need?