any design tips to reduce the shoot-through current

[chang830]

we are designing a driver with CMOS process. We found the shoot-through current is a bit large. This increases the total power consuption. I want to know any design tips to reduce this current?

Thanks in advance

 

[rfsystem]

Solution:

Drive the PMOS and NMOS independend. Switch on only the last output device if the gate of the other last output device has switched off. So you enable the switch on of one output device of the gate of the other is near the threshold voltage. You use logic for these locking circuit. Further "standard" techniques" are delayed switch on. So the output stage is sliced into e.g. 8 devices and is switched by an inverter delay chain. Switch off is done in parallel, so much faster. That minimize the di/dt for charge/discharge. If you swicth off there is no di/dt limit because the current has gone to zero already.

 

[chang830]

Solution:

Drive the PMOS and NMOS independend. Switch on only the last output device if the gate of the other last output device has switched off. So you enable the switch on of one output device of the gate of the other is near the threshold voltage. You use logic for these locking circuit. Further "standard" techniques" are delayed switch on. So the output stage is sliced into e.g. 8 devices and is switched by an inverter delay chain. Switch off is done in parallel, so much faster. That minimize the di/dt for charge/discharge. If you swicth off there is no di/dt limit because the current has gone to zero already.

Thanks for the helpful reply. One guy in our team proposed a solution which add a small series resistor(~30 Ohm) at the one gate of the output device to provide a dealy. I have the concern this will add considerable noise/jitter at th eoutput. Pls. comment!!! Thanks a lot.

 

[mdcui]

Adding delay on both input signal rising edge and falling edge shall not help, I think, because you still can not avoid turnning P/N device on together for a short period of time, we have to seperatly handle rising edge and falling edge for the P and N side to avoid that.
how did you add the resistor to overcome this problem?

 

[chang830]

Adding delay on both input signal rising edge and falling edge shall not help, I think, because you still can not avoid turnning P/N device on together for a short period of time, we have to seperatly handle rising edge and falling edge for the P and N side to avoid that.
how did you add the resistor to overcome this problem?

Adding the series resistor only one of the output devices,i.e., the P mos or N mos.