Hi,
In my design, with the area considerations, I need the overlaping of via1 and contact, I cehcked the design rule, it gives no infotmation on it. And I also communicated with the foundry, they seemed also not sure about it.
i guess there would be no problem in 0.35um technologies.
to be sure, make a simple layout that has the diff, contact, metal, 1st via, and 2nd metal layers. overlap those layers and check it with DRC.
i guess there would be no problem in 0.35um technologies.
to be sure, make a simple layout that has the diff, contact, metal, 1st via, and 2nd metal layers. overlap those layers and check it with DRC.
i guess there would be no problem in 0.35um technologies.
to be sure, make a simple layout that has the diff, contact, metal, 1st via, and 2nd metal layers. overlap those layers and check it with DRC.
That is process dependent. Is the process planerized? Are the contacts and vias filled (tungsten plugs)?
I have worked on two 0.4um processes 1 which allowed stacked vias and contacts and the other didn't. It should be checked by DRC if it is allowed or not, if it doesn't it isn't a well wretten DRC.
That is process dependent. Is the process planerized? Are the contacts and vias filled (tungsten plugs)?
I have worked on two 0.4um processes 1 which allowed stacked vias and contacts and the other didn't. It should be checked by DRC if it is allowed or not, if it doesn't it isn't a well wretten DRC.
As I know,the contact and via stack depend on the FAB CMP process stability,It's will induce reliablity, yield etc.....,but 0.35um process have to conquer this issue.
I have used various 0.35um process so far none of them forbid the overlapping of Contact and Via. And If it doesn`t violate DRC after execution I think there is no problem with that.
i think that it won't be a problem only if you don't intend to connect the poly or diffusion to other metals than metal 1 ...
in other words...the contact is used to connect poly or diffusion to metal 1
if there's a via12 on top of the contact...and you don't intend to connect, then there will be a problem...if not then it should be okay
Hi ,
If you are very doubtful of via1 stacking over cont, then better go ahead and place it in one place and run drc checker. The checker would flag an error if does not support it. But usually via stacking over cont is very much permissible
First of All...As a good layout engineer we should not always depend upon DRC. Yes I will agree if DRC is not reporting any errors it's correct as per check. But the main aim of a layout engineer is to increase the yield.
Some one told that In some technologies it is allowed to use stacked VIAs and in some technologies it's not allowed. If aloowed it's ok...If it's not allowed...let's discuss why like that.
I have some concept regarding that. Upto now I worked on 350nm to 65nm. Some foundries will allow the stacked metal but some not.
Concept: Let's take some exapmle. I am using 4 metals in my layout. I need to connect my transister from M4. Now I am using Contact, V1, V2, V3 at the same place. What happend now, whenever I am using like that, at the same place I am putting holes and pouring some layer(I don't remind the exact metal) for current passing. Now when we use contact, V1, V2, V3 stacked. Contact will be having more stress from the V1, V2, V3 metals. If you know the concept Metal Sagging, you will get to know. That's why we need to try to reduce the stacked metals.
At tha same time you are going to high current directly to the transistor. It my cause to increase the electromigration too...