Anti-reverse diode for PMOS?

[ysz]

pmos body diode

I'm designing a power ic, there has a power pmos in it , but if the vdd down to 0V, the pmos will be destroyed, I don't know why?
and I don't know how to add a anti-reverse diode for the pmos, could someboby tell to me, tks very much!

 

[aryajur]

How is the PMOS connected? Also what is the voltage at the gate of the PMOS when the VDD goes to 0? Check if you exceed the gate oxide breakdown voltage..
What is the other suppply line - 0v?

 

[ysz]

sorry，the pmos drain connect to a battery, when vdd goes to 0V, the dattery supply a reverse current to pmos, it will destroy the pmos, I don't know why, and I don't know how to solve this problem also.

 

[arsenal]

the bat voltage is too high for the pmos
u may have to use some kind of floating body technique to let the body to charge to the bat voltage to prevent the breakdown

 

[ysz]

arsenal, thank you.
but the battery voltage is 4.2V only.

 

[Hughes]

I think it is because you tied the pmosfet's bulk to vdd. When vdd goes to zero, the bulk of pmosfet will go to zero, thus the drain diode will be forward biased to 4.2 volts. You should dinamically select the bulk connection.

 

[ysz]

if the power source take away, the N-well's voltage will be Vbattery -0.7V, the current will flow from drain, through n-well to n+, arrive vdd, which reason will cause the pmos destroyed?

 

[Hughes]

Refer to your figure, the bulk of pmos (Nwell) is tied to vdd. When Vdd is tied to ground (0V), and battery (D) voltage is 4.2 V, the diode formed by P+Diff Drain and Nwell if forward biased to 4.2V. This leads to a large current sufficiently to damage the device.

 

[arsenal]

ysz, use floating body, and let it be charge to 4.2v when vdd is 0,

 

[tsanlee]

YSZ:
You must design a reverse protection circuit in this application.
when VBAT>VDD ,the control circuit powered by VBAT,and PMOS body diode (n-well) switch to the highest voltage . this can make sure the PMOS safe in any condition. Or the short current will damange you PMOS(VBAT->Diode->VDD).

 

[ysz]

Refer to your figure, the bulk of pmos (Nwell) is tied to vdd. When Vdd is tied to ground (0V), and battery (D) voltage is 4.2 V, the diode formed by P+Diff Drain and Nwell if forward biased to 4.2V. This leads to a large current sufficiently to damage the device.

Hi,hughes!
Vdd should be Vbattery-0.7V, for example, the current of Vdd =10mA when Vdd=5V, when power down, it shoud be 10mA or less, and Vdd should be 3.5V I think?

Added after 58 minutes:

To arsenal & tsanlee, do you know the principle of this structure?
a kind of pmos:

 

[Hughes]

Hi ysz,
The schematic view above doesn't match with the cross-section view you posted earlier. The diode should be reversed and short-circuited according to the cross-section view. Another diode between bulk and drain isn't shown in this figure.

 

[ysz]

Hi ysz,
The schematic view above doesn't match with the cross-section view you posted earlier. The diode should be reversed and short-circuited according to the cross-section view. Another diode between bulk and drain isn't shown in this figure.

Hughes, you are right! The picture I first posted is a normal pmos, and the second is saw in many datasheet for anti-reverse voltage. I do'nt know how to implement it. could you show me the section of the second pmos? thank you very much!

 

[Hughes]

I think it is hard to implement such a diode in standard CMOS process. Maybe the only available diode is P+ diffusion to Nwell diode, but this represents a considerable large substrate current due to the parasitic pnp transistor.
Instead, I post another schematic for your reference.