Well, of course your friends Mr. Googlez and Ms. Wiki would
have plenty to tell you about it.
"Antenna effect" refers to plasma damage during processing.
A localized charging and gate current is imposed by dry etch
(positive charged ions) which can cause reliability degradation,
develop mismatch beyond the natural process scatter, or outright
rupture a gate deep in the guts (unlike pin applied ESD which
usually just hammers the I/Os).
The periphery of a metal layer determines the "aggressor"
charge / current. So long skinny lines and large area (hence
large periphery) are the threat sources.
The area of attached gate oxide (along with the population
of defects) determines how that current will be concentrated,
what current can be withstood. Gate oxides leak some, with
no impact (esp. newer nodes where gate tunneling is a major
thing anyway). More current can only be taken by voltage rise
and oxide rupture eventually, hot carrier damage leading up
to it. More oxide area tolerates more current so tolerates more
attached metal periphery.
An antenna feature "exercises" everything that is attached to it
from below. The stuff above, hasn't happened yet. So one key
mitigation is to break low level traces often and jumper them
with a higher level segment and vias. Floating segments do
nothing. Short connected-to-gate segments do nothing. You
would be better off with 5 1000um met1 segments with 4
2um jumpers connecting them, than 1 5000um met1 trace.
A last-ditch remedy is the "antenna diode" which can be
added to a line to ensure that there is an ohmic path to the
substrate, draining charge as it comes in. Not practical on
SOI (no chuck / substrate access) but common in JI digital
technologies.