antenna effect concern in layout

[mary96960]

antenna effect

I have noticed that there are Polysilicon antenna,Contact antenna,Via antenna and Well antenna, other than Metal antenna. What are these antennas refer to? How to correct these antenna violations in layout? I have well antenna errors with Calibre DRC check.
Thanks.

 

[hanslem]

antenna effect layout

hello mary, I thought the antenna check is only to protect the polysilicon from surg voltages during fabrication? Well antenna?? I don't know but maybe other members could answer your question for us to know... best regards...

 

[mary96960]

well antenna

For me, it is also the first time to enccount.
Hopefully, some one can help...

 

[pvnk]

how well antenna

hi mary,

antenna error happens when the ratio of area of X, where x can be a metal rout, a local interconnect rout( type of low resistance poly used in some of the processes to do small length connections and voltage distribution like in substrate conn etc.), to the area of gate conected to it increases beyond the FAB mentioned ratio.

the problem here is, during Reactive ion beam/ion beam etching, this structure connected to the gate will gather enough charge to damage the dielectric of gate, ie, thin oxide. so your problem can be reduced by decreasing the area ratio.

To find out what exactly is the antenna error in your context, you better refer your rule file. sometimes, soft and antenna checks are clubbed together.

hope it's clear.

 

[mary96960]

antenna effect in layout

Thx.
My understanding is that antenna rule only cares about the ratio of metal to gate area. Why my design rule involves well\vias\ in?

 

[pvnk]

atenna effect

i'm not sure about it. usaully it bits you only with long lower metal lines touching gate. your FAB is the right contact to clear this doubt. ( i expect that you got your rule file from them)

 

[Fom]

touching gate drc

the problem here is, during Reactive ion beam/ion beam etching, this structure connected to the gate will gather enough charge to damage the dielectric of gate, ie, thin oxide. so your problem can be reduced by decreasing the area ratio.

That's right and that is happened in final etching stage. When you almost finish etching and proceed it litlle bit more for insurancy. Before that all metal elements still connected with each other and the charge current can easily leak. But in this final stage the sctructure has some floating Metal islands those have connection to gate with thin oxide. Because top of metal is isolated by photoresist the charging current flows through perimeter of these floating area. The less gate capacitance the higher voltage can reach gate voltage. So the ratio of metal island perimeter to gate area is key parameter.

The same situation can by during via etching. In final stage when you alredy open via to metal floating island the churge current start increase gate voltage. Before that the metal is isolated by oxide. But in this case current flow trough open vias. So VIA area to gate area is key parameter now.

Then next metal. Again perimeter to gate area.
But if floating island becomes connected to any drain or source area it should be excluded from consideration because of junction leakage.

 

[analayout]

nwell antenna

hi
well antenna means charging of NWELL with respect to gate durinig fabrication
if the nwell to substrate leakage current is high enough compared to gate leakage it will destroy gate
the solution is make nwell to substrate leakage less than gate leakage
for this generally the nwell is tied down to sustrate using m1 that means we r creating a reverse biased diode
regards
analayout

 

[leohart]

layout anten

hi
well antenna means charging of NWELL with respect to gate durinig fabrication
if the nwell to substrate leakage current is high enough compared to gate leakage it will destroy gate
the solution is make nwell to substrate leakage less than gate leakage
for this generally the nwell is tied down to sustrate using m1 that means we r creating a reverse biased diode
regards
analayout

sorry analayout,Can you elaborate you comment?
I don't know why the nwell will be charging to gate during fabrication?And what's the relationship between nwell to sub leakage current and the gate leakage?Isnt it the voltage damage behind the antenna rules?:?::?:

 

[mary96960]

www.edaboard.com ftopic238568

Thx, all.
I have well antenna definition as followed:
Well Antennas
Increased PFET gate leakage currents and reliability time-dependent dielectric breakdown (TDDB) failures were observed in test structures tied to the substrate with an n+ diode. The assumed cause is charging of the n-well with respect to the gate due to large antenna connections (for example, pads with many vias). Well
antennas such as these can result in gate oxide damage and reliability failures. Thicker gate oxides, like DG
and EG, are more likely to be affected than thin gate oxides due to lower leakage levels. If the n-well to substrate diode leakage level is high enough, charge flowing into the substrate can prevent gate oxide damage. This counteracts the very low leakage level intended for the n-well. Tying the n-well to the substrate using a diode with a higher leakage level than the n-well to substrate diode is an effective solution.
In principle, well antennas might similarly affect NFETs in a triple well, but these structures are not yet available.
In the meantime, triple wells should be tied to the enclosing n-well.
Tying the n-well to the substrate is inherent in most circuits. For example, an inverter connects the n-well to
the substrate using its p+ drain to its n+ drain, respectively.

My question is how to tie the n-well to the substrate using a diode.

 

[analayout]

layout antenna

hi mary
take the m1 from the blk of pmos to outside of nwell then put an m1to RX contact
i think nw u r clear
ragards
analayout

 

[mary96960]

antenna effect on poly etch

analayout ,how? To where should I connect the m1 of the blk ?
Thx.

 

[analayout]

antenna well

hi
generally NW is connected with VDD through substrate contact
take m1 from the sustrate & route it in outside of Nwell then put a m1 ti RX contact
this should be outside of the Nwell .
the contact is N+ diffusion so by this actually we r creating a reverse biased diode
hope that ur clear nw
regards
analayout

 

[mary96960]

antenna effect

Sorry, i still do not make sense.
I guess a pic can help.
BTW, i think normally we connect NW to VDD via NW contact by m1.Are you proposing using a N+ diff outside NW, instead of inside it,and connecting it to the souce of the PMOS inside NW? So, what the voltage potential should I connect to N+ diff, VDD also?

 

[mary96960]

layout antenna effect

Sorry, it should be like this.Am i right?

 

[analayout]

layout antenna definition

hi
we need to connect NW to N+ diffusion
so on the Nwell we r placing a N+ diddusion (m1 to RX)contact
from that point we r routing m1 to outside of nwell & put a m1 to RX contact(N+ diffusion)
as shown in the attachment
hope that nw ur clear
regards
analayout

 

[mary96960]

layout antenna errors

Thank you very much!!
MOST of the errors gone,except for one, which is a NMOSCAP formed by diff, N+ implant, NW,ect , and having p+ pickup outside of NW.How to add reversed biased Diod in this case.

 

[analayout]

antenna effects + chip layout

hi
i didnt get it
could you expain
regards
analayout

 

[mary96960]

what is metal antenna violation in layout

I mean the same DRC violation happened on a NMOS formed Cap. That is created by N+diff, poly, ct ,m1, NW. To solve, I have added a N+ diff inside the NW as NW pickup and another N+ diff outside it to creat the reversed biased diode. Then the violation is gone. But I am wondering is it correct for doing so on a NMOSCap?Cause in the original layout, the NW is floating.
Thanks.