AND gate for clock gating

[sun_ray]

What are the drawbacks for using an AND gate for clock gating?

 

[jamespond]

When input not in phase with the clock pulse, the output clock possible contains a fractured cycle.
For switching clock, you can use 74hc74 or similar.
Pin clk as clk
Pin d as gate
Q or _Q as output.

 

[bright8848]

If the clock enable signal de-assert when clock signal is high, a glitch will apear.

 

[sun_ray]

That is known that glitch is an issue. Do you find any other issues? The thread was started, if you can point for any other issues.

 

[vkansal12]

There is not any other issue. If you can get a complete symmetrical clock pulse out of the AND gate, you need not to worry.

 

[owen_li]

As I know, clock gating hold check on the AND gate will be much harder to be met than using ICG cell (intergated clock gating cell).
coz, we should guarantee the clock pulse will be not clipped by the early arriving clock gating enble signal.

 

[bright8848]

As I know, clock gating hold check on the AND gate will be much harder to be met than using ICG cell (intergated clock gating cell).

Can you give some detail about this issue?

 

[vkansal12]

If you use an AND gate to gate a clock signal, you have to ensure that the enable signal changes only during the period when the clock signal is low. If enable changes during high clock period, you will get a clipped clock pulse. You can verify by drawing waveforms. If enable signal launches from a positive edge-triggered flip-flop, we get a half cycle hold check which cannot be met in real scenario. So, if you are using AND gate, you have to ensure enable launches from negative edge flop.