Analog Oscilloscope to capture logic glitches

[lewisP]

How do I set up a analog oscilloscope to capture logic glitches?

I have tried using normal and single sweep trigger

 

[D.A.(Tony)Stewart]

Remove probe tip and ground clip and setup two pins close to source to connect probe barrel and pin to gnd and signal.

Then use DC coupling , normal trigger, threshold set to 1.3V or whatever logic in between and choose+ trigger for normally low levels, and wait for glitch.

 

[lewisP]

why use normal trigger and not signal sweep mode? This will capture and save the nanosecond glitch?

 

[D.A.(Tony)Stewart]

Normal only triggers when glitch exists, vs auto
or use one shot

 

[lewisP]

Where can Glitches come from mostly? Any logic TTL or CMOS chips that cause common Glitching problems?

 

[chuckey]

Set the time base to slow, adjust the trigger level so it does not run on single sweep. Now adjust the trigger level until the time base runs. Increase the time base speed until the "glitch " is visible.
Frank

 

[Gorgon]

There are several 'basic' sources for glitches in logic, in any logic family.

Noise from a badly decoupled supply voltage can be one typical source. The different logic families have slightly different requirements here, but in general it is the same.

Long/slow shifting signal flanks wil open for any noise in the system and give glitches. You control this with adding/using Schmitt trigger input gates.

If you have a very 'dirty' input signal and the schmitt trigger does not take care of the input glitches, you may need to add a debounce circuit on the input.

If you design complex logic with a number of gates, you may(will) have glitches when the different signal combinations are delayed differently through the network of gates. That is why it is normal with a defined clock or gating signal to sync the result.

If you use ripple or async counters, you may have undefined combinations on the outputs during counting, creating glitches in the following decoded logic. This is a bigger problem when the clock frequency are getting higher, and the inherent delay inside the ripple counters get more prominent. To eliminate this, use a synchronized counter.

So, the general answer is to always use defined states and stable inputs before executing a change in the logic state of the outputs.