Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

analog multiplier topology

Status
Not open for further replies.

simplybharath

Junior Member level 2
Joined
Apr 22, 2009
Messages
21
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
1,400
here the 4 PMOS transistors are in saturation and all other NMOS transistors are linear. can anybody explain me how this multiplier works ? if anybody could explain it with equations it will be really helpful

well the o/p is taken as vo1-vo2= (kp/(kn*km))*(xy) [/img]
 

zopeon

Member level 2
Joined
Sep 12, 2008
Messages
51
Helped
6
Reputation
12
Reaction score
1
Trophy points
1,288
Location
India
Activity points
1,612
Hi,
This regards to your question on linear MOSFET analysis and the question on circuit. You have to do small signal analysis as X is dc and x is your sir ac signal. ( I assume) You can consider M1 as Resistor and N1 also as resistor (but variable) . Where the variable value for N1 will depend on y (for ac) and base resistor value will depend on Y. I have uploaded the small signal model for half the circuit. I hope its correct.
Hope this helps

- zopeon
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top