analog layout design

[jirika]

Didn't quite understand it. Can you please explain it a bit more?
And how the capacitance (parasitic) slow the clock?

Yes, not frequency but just rising and falling edges. If you'll add shielding (another wire in parallel) you'll add capacitance, right? And I'm quite sure you are aware of how voltage is rising if you're charging capacitance, right? So instead of nice and sharp edges you will have rounded edges.
The ultimate case would be when parasitic cap would be so high that you are not able charge it enough before the oposite half-period of clock will come
But as I said the best shielding is no shielding at all. Well in better words keep all wires far away of any noisy (clock) wires. And parasitic cap is enemy of clocks.

 

[erikl]

Didn't quite understand it. Can you please explain it a bit more?
And how the capacitance (parasitic) slow the clock?

Additional (parasitic) capacitance is like higher fanout: it can't change the frequency, but increases the edge rise and fall times (skew rate ~ 1/C).

 

[protonixs]

Thumb of rule when it comes to shielding: Connect the shield where the line is reference to. Example: If the line you want to shield is VP with respect to VSS, connect the shield to VSS. If the the line you want to shield is VCOMP with respect to AVSS, connect the shield to AVSS, and so on.
One more thing to note, shield are connected to ground, be it AVSS, VSS, DVSS, GND, etc. and NOT to VDD/AVDD/DVDD.
Reason why it is not recommended/advisable to connect shields to VDD: VDD is noisier than VSS/Ground

 

[Danielle712]

Hi All,

I am getting ready to go on an interview for a layout position. I have 17 years experience in power management, but my experience is limited to designs upto 1Mhz range. The position requires experience using inductors and varactors which I have none. I have been doing lots of research on both devices and don't have a great grasp on the logistics. I am use to custom layout and packing in my chips which I think is not the case when using inductors. Can someone please enlighten me on the layout techniques of inductors. Also, some details about varactors. I believe I have a better understanding of varactors, but would be best to make sure.

Thanks in advance. Danielle