analog layout design

[bau69]

how we can sheild the sensitive signals when the clock is crossing the sensitive signal? pls help me

 

[circuitrookie]

just put ground or supply (depending on which your signal is reference to) around your signal.

 

[bau69]

just put ground or supply (depending on which your signal is reference to) around your signal.

what is use of putting gnd or supply around it

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just put ground or supply (depending on which your signal is reference to) around your signal.

let say example if sensitive signals is in m3 and clock is in m1, which is perpendicular to sensitive signal i.e m3. what should i do to sheild the sensitive

 

[Ow@i$]

Provides isolation from external interference... as well as absorbs all interference generated by the signal itself, thus protecting external circuit...

 

[erikl]

... if sensitive signals is in m3 and clock is in m1, which is perpendicular to sensitive signal i.e m3. what should i do to shield the sensitive

In this case you could shield it by a large grounded metal patch on m2 between the crossing.
Otherwise use adjacent parallel clock and clock_bar lines with similar slew rates.

 

[circuitrookie]

what is use of putting gnd or supply around it

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let say example if sensitive signals is in m3 and clock is in m1, which is perpendicular to sensitive signal i.e m3. what should i do to sheild the sensitive

the way the clock affects your signal is through coupling, so by adding a ground between the two line, the coupling can only go to ground and not to your signal.

for your case, i am not sure what you mean by perpendicular, but even if they are routed parallel to each other you can simply place a M2 ground between them. normally for sensitive signal you want to put grounds next to them on the same level too like GND signal GND and you can enclose it by placing gnd on top and on bottom as well.

 

[dick_freebird]

Crossing orthogonally minimizes the coupling. Running the
signals parallel for any distance, increases it. I doubt that
a 90-degree crossover results in much Cxy - and if your
circuit is sensitive to that extent, you're probably in all
kinds of trouble.

 

[Teddy]

I recommend to run GND line in distance of 1-2um left/right from your CLK line This will shiled nicely the signals parallel with CLK and also minimizes the capacitive load oon CLK line. THEN run PEX with Calibre and run simulation. You should see very well how the shielding works.
I do not like to put metal above/bellow CLK line due to added capacitance but sometimes there is no other way. There was i believe patent from MOTOROLA which described the CLK shileind with "railroad" track layout. In other words you dont put solid metal on top/bellow but connect lines on left and right from CLK with ie 1um wide metal bars. Spacing will be about 2um. That helps the shielding since it braks the field (feel free to run the math) but minimizes the cacitance between lines.
This all is true if your metal spacing in x direction >> metal spacing in z direction (oxide thickness)

 

[VLSI_Learner]

How to decide - we need to shield both sides with vcc or vss or one side vcc and the other side vss?

 

[erikl]

How to decide - we need to shield both sides with vcc or vss or one side vcc and the other side vss?

vcc or vss doesn't matter: any low impedance virtual ground node is fine for shielding.

 

[VLSI_Learner]

But why the designers specify it? Sometimes ask to shield both sides with vcc or vdd or sometimes one side vcc and other side vss.
And one more thing, if two different signals are in different metals, I don't think there is any need of shielding. Suppose there are two signals - one high frequency clock signal in m2 and other critical signal in m3.
The critical signal don't need any shielding to get protection from m2 clock signal.
Because during fabrication all m2 are deposited first, then on top of it insulator is placed, and then on top of it m3 is deposited, so the isolation is already taken care of.

 

[erikl]

But why the designers specify it? Sometimes ask to shield both sides with vcc or vdd or sometimes one side vcc and other side vss.

May be because the designer knows which node is easier to reach. A (good) designer thinks about the layout of his design!

... if two different signals are in different metals, I don't think there is any need of shielding. Suppose there are two signals - one high frequency clock signal in m2 and other critical signal in m3.
The critical signal don't need any shielding to get protection from m2 clock signal.
Because during fabrication all m2 are deposited first, then on top of it insulator is placed, and then on top of it m3 is deposited, so the isolation is already taken care of.

Isolation doesn't mean shielding from capacitive RF coupling!

 

[VLSI_Learner]

Yes, forgot about that capacitive RF coupling. In that case we need shielding regardless of any metal layer. Other than the capacitive coupling is there any other way that the sensitive signal can become noisy due to the influence of high frequency signal?
You mentioned that the designer knows which node is easier to reach. Can you explain it a bit as I can't make out what the edge is achieved with the position?
Please explain.

 

[erikl]

Other than the capacitive coupling is there any other way that the sensitive signal can become noisy due to the influence of high frequency signal?

Inductive coupling by current flow.

You mentioned that the designer knows which node is easier to reach. Can you explain it a bit as I can't make out what the edge is achieved with the position? Please explain.

A (good) designer will have a certain imagination (and possibly will even provide corresponding instructions to the layouter) on which metal layer which power supply node is easier reachable for shielding.

 

[VLSI_Learner]

I can understand the capacitive coupling, but can't make out how inductive coupling affects here?
By the way what is inductive coupling?

 

[erikl]

By the way what is inductive coupling?

This is basic electrotechnics - I'd suggest to study the appropriate books - or even G00gle. It's not the forum members' mission to teach you electrical or electronics basics!

 

[jirika]

Btw if you'll add shielding you'll also add parasitic cap between clock and shielding wire. Therefore you'll slow this clock.
So I usually place shield just where it's needed.

 

[erikl]

Btw if you'll add shielding you'll also add parasitic cap between clock and shielding wire. Therefore you'll slow this clock.

Actually not the clock (frequency) itself, just the clock edges.

So I usually place shield just where it's needed.

True: just at the crossings, as the OP asked.

 

[VLSI_Learner]

Actually not the clock (frequency) itself, just the clock edges.

Didn't quite understand it. Can you please explain it a bit more?
And how the capacitance (parasitic) slow the clock?

 

[venkat03ie38]

If it is critical signal you want to sheelding both vertical and horizontal