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Analog and digital ground and supply voltage seperation in IC

Junus2012

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Hello friends,

I have digital and analog part in my chip design,
It is usually recommended to separate the supply lines and ground from each other for noise consideration.
However, how can I physically separate the ground when both the digital and analog parts are realized on the same substrate (I am using PWELL technology)?

I have tried that by making VDD GND pins for analog circuit and gnd! and vdd! for digital circuits, and in the time of layout verification it complains that gnd! and GND are shorted and can not even pass the LVS,
I conclude that separation is schematic while it looks fine, but physically not possible, unless there is a proper way of separation which I want to ask you about it.

Thank you
Best Regards
 

martinnl

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As much separation as you get in schematic, infinit, is not possible.

What you can do is to separate them in a few different ways.

If deep nwells are available you can use them or otherwise make low ohmic guard rings that pick up substrate noise so it does not propagate to the analog part.

Then a proper grounding scheme using, for example, star connection or even separate pads could be helpful.

Regarding LVS, you could use sub cuts to fix those but they are only a help and the actual connection will still be there.
 

guntherleet

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using ! make global net and is not recommended, you can use vdda and vdd for example to represent analog domain supply and digital domain supply.
there are layout layers designed for this issue of separated supplies that enable you to connect to different substrates in the same layout(PSUB2 if I'm correct).
 

dick_freebird

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I like to let the substrate be its own net but at some
point in the verification process you will need to tie
it to some pin and chip net. I like to use a presistor
from sub! to a pin driven vss net, which will collapse
the sub! nore into the named net for verification but
allow you to express as much of the supply net detail
as you choose (distributed R, L). No DC current should
flow through the substrate. Keeping things separate
in the schematics will let you inspect that (if you have
embedded the net parasitics detail, to see I*R and
L*dI/dt effects).
 

timof

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Quite often, analog and digital ground nets have to be connected to the same pad / ball.
In this case, to de-couple these two ground, one needs to minimize the common resistance between these domains. Common resistance is voltage appearing on one domain when a current is injected into the other one.

This task may not be trivial when number of metal/via layers in the BEOL is large.
 

Junus2012

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Thank you guys,

My issue is solved after your help, I am now using the SUBCUT layer to define the region of different net connections. To pass the LVS rule I ws recommended to use S_res from the prim-lib of my technology.

I would say even in the document is written that there is no big advantages of ground separation, but little improvement in the noise rejection. I have explored some of the PCELLs from the foundry and I have found that many times they used to merge the analog and the digital ground together.

Thank you
 

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