An inverter placed into scan chain path

[jirika]

Hi all,

i'm trying do a scan chain at a simple design with 16 flip-flop with Synopsys Design Compiler.
When a scan chain is created I looked at schematic and saw that between a two FF (their Q output and TI input) is placed an inverter.
So without knowing this when I will try send a logic vector into the first FF and wait for the vector will run through all FF I'll get a wrong vector at the end.
Anyone noticed that behavior or know why it's happening? I'm looking into manuals but still nothing.

 

[kornukhin]

It's normal practice to put invertor/buffer into scan chain. When you load test vector in chain ATPG tool knows that values will be inverted on such invertors. The same happends when you unload captured test vector.
You shouldn't generate test vector by hand. Use TetraMax (FastScan, Encounter Test...) for automatic generation. Tool knows about this invertor.
You can read "Scan design 10 tips" (ask Google).

 

[jirika]

Thank you kornukhin. I'll try that TetraMax tool.