an interesting problem in conformal

[mic_huhu]

hi,all

I faced a so strange case. when I checked my ECO netlist against my original RTL code , they are equal ! but the two netlist are nonequal and the two RTL are nonequal too. why?

I have tried servial times to verify the ECO netlist . it is right.

who can tell me why?

thanks

Johnny

 

[anjali]

two designs may be functionally equal, but may not be structurally equal.

in functional verification, we can check some conditions. but there may be so much logic untested or unequal

 

[mic_huhu]

but .the two design are different in performance,which can be proved by FPGA.

module check can check it out. why the full system check can't ?

I have try several times . the results are same.

the systhesised netlist (came from Eco RTL ) are equal with ECO netlist . no equal with NonEco netlist.