an even smarter shift register

[shaiko]

Efforts from a previous post yeilded this "smart" rx shift register.
It receives data serially through "input_bit" and shifts it conformally a "data_width" number of times either msb or lsb first controlled by "shift_direction".

entity rx_shift_register is 
                                                                                														
port				    						
( 				        						
	clock : 		in std_logic ;	
	reset :		in std_logic ;
	shift_now :	in std_logic ;
	shift_direction :	in std_logic ;
	input_bit :		in std_logic ;
	data_width :	in unsigned ( 3 downto 0 ) ; 
		
	data_out : 		buffer unsigned ( 7 downto 0 )
) ;	 
                                       
end entity rx_shift_register ;

architecture synthesizable_rx_shift_register of rx_shift_register is

begin 

  process ( clock , reset ) is
       begin
            if reset = '1' then
                 data_out <= ( others => '0' ) ; 
            elsif rising_edge ( clock ) then
                 if shift_now = '1' then
	      if shift_direction = '1' then
	           if data_width > 0 then
	                data_out ( 0 ) <= input_bit ;
		for i in data_out ' length - 1 downto 1  
		loop
	                     if i < data_width then       
		          data_out ( i ) <= data_out ( i - 1 ) ;           
		     end if;                         
	                end loop; 	
	           end if ;	
	      else
                           for i in 0 to data_out ' length - 1 
	           loop
	                if i = data_width - 1 then       
		     data_out ( i ) <= input_bit ;                  
		elsif ( i < data_width - 1 ) and ( i < data_out ' length - 1 ) then             
		     data_out ( i ) <= data_out ( i + 1 ) ;           
		end if;                         
	           end loop;   
	      end if ;
                 end if ;
            end if ;
       end process ;	

end architecture synthesizable_rx_shift_register ;

Now, I want to design a tx shifter register on the same principles as the above.
This is how I see the entity...

entity tx_shift_register is 
                                                                                														
port				    						
( 				        						
	clock : 		in std_logic ;	
	reset :	                in std_logic ;
	shift_now :	in std_logic ;
	shift_direction :	in std_logic ;
	data_width :	in unsigned ( 3 downto 0 ) ; 
	data_in : 		in unsigned ( 7 downto 0 ) ;
	
	output_bit :	buffer std_logic ;	
) ;	 
                                       
end entity rx_shift_register ;

Please help me write the VHDL process.

 

[mrflibble]

Is that the "do my work" kind of help? Or the "gimme some suggestions" kind of help?

Well oh alright, I'll give you one line then...

Change "end entity rx_shift_register ;" to "end entity tx_shift_register ;"

There we go.

As for suggestions, your other code looks like you are capable of writing okay vhdl code. So gogogo! You can always ask specific questions.

As for another suggestion: write down detailed specs. Especially if you want people on a forum to give you advice then it helps if you communicate what the hell the tx_shift_register thingy is supposed to do. And yeah yeah, it's supposed to shift. So that'll give us the freedom to conjure up a random entity that shifts some stuff, and say hey shaiko, lookie here! your tx_shift_register thingy. And then you get to say "but but but, this is not what I want". And then we get to say "well wtf?!? it conforms to your loose specs. And we get to say ""well could you please be more specific. And then you get to give a vague clarification. And then there follow 10 posts, after which a half decent spec has been puzzled together.

And that is all good because we all know engineers LOVE a good puzzle.

Well either that, or just give the clear specs now. Might speed up the process. ;-)

 

[shaiko]

Change "end entity rx_shift_register ;" to "end entity tx_shift_register ;"

Hey, that's a good start!


Now, about the specs.
I was afraid that the post is already too long - not far away from the point of being boringly long...
But now, that I got the attention of at least one interesting reader - I can proceed !

1. The register gets data parallel data, from a neighboring entity that controls it
2. It decides wheter to shift the data msb or lsb first according to the "shift_direction" direction control signal.
3. The tricky thing is that "data_width" controls the active width dynamically (as with rx_shift_register...)

An example:
The controlling entity asserts the following signals to the tx_shift_register entity.
"11001100" - at the "data_in" input port
"0101" - at the "data_width" input port (integer 5). This sets active the 5 rightmost bits (marked in red) of "data_in" - hence "11001001".

Every time "shift_now" is asserted - the active portion of "data_in" is shifted (either right or left).
if shift direction = '1' then it will look like this:

"11001001" shift "10010010" shift "00100100" shift "01001000" shift "10010000" shift "00100000"
Because "data_width" is set to integer 5 and we send msb first - the "output_bit" will always stobe the fifth bit.

What do you think about this :

entity tx_shift_register is 
                                                                                														
port				    						
( 				        						
	clock : 			in std_logic ;	
	reset :	            in std_logic ;
	load_data :			in std_logic ;
	shift_now :			in std_logic ;
	shift_direction :	in std_logic ;
	data_width :		in unsigned ( 3 downto 0 ) ; 
	data_in : 			in unsigned ( 7 downto 0 ) ;
	
	output_bit :		buffer std_logic ;	
) ;	 
                                       
end entity tx_shift_register ; -- thanks mrflibble!

architecture synthesizable_tx_shift_register of tx_shift_register is

signal shift_register ( 7 downto 0 ) ;

begin

	output_bit <= shift_register ( to_integer ( data_width ) - 1 ) when shift_direction = '1' else shift_register ( 0 ) ;

	process ( clock , reset ) is
	begin
		if reset = '1' then
			shift_register <= ( others => '0' ) ; 
		elsif rising_edge ( clock ) then
			if load_data = '1' 
				shift_register <= data_in ;
			elsif shift_now = '1' then
				if shift_direction = '1' then
					shift_register <= shift_register ( 6 downto 0 ) & '0' ;
				else
					shift_register <= '0' & shift_register ( 7 downto 1 );				
				end if ;
			end if ;
		end if ;
	end process ;

end architecture synthesizable_tx_shift_register ;

 

[j_andr]

may be this gives a hint ?

 if ( data_width != 0 )
 begin
   if ( shift_now )
   begin
     if ( shift_direction )
       < shift_right >
     else
       < shift_left >
     
     data_width-1
   end
 end

---
ja

 

[FvM]

output_bit <= shift_register ( to_integer ( data_width ) - 1 ) when shift_direction = '1' else shift_register ( 0 ) ;

Yes, looks good.

Like mrfibble I don't see a particular problem involved with a configurable tx register, except for writing and debugging the code. Personally, I have a few thousand lines left for me, too.

 

[mrflibble]

Seems fine to me. About this bit ...

	output_bit <= shift_register ( to_integer ( data_width ) - 1 ) when shift_direction = '1' else shift_register ( 0 ) ;

That part gets executed no matter what the value of load_data is. That's the plan? Or should the output_bit be handled differently when loading data?

Or do you define clever stuff like "well, you should put shift_direction to 0 when you want to load data". Because yes that would take care of that, and no I wouldn't recommend it. After all, your module will be used by humans, ;-)


Anyways, overall it looks good. I'd say put it through a quick testbench to see if it does what you want.