vinhphuong
Newbie level 5
We are verifying an AMBA-based SOC.
Verilog full processor is not available now.
But all of other components on the system like AMBA bus, UART, Timer,..., we use designware from Synopsys (so it is available now).
Now we want to test the interaction on the AMBA Bus first (while waiting for the full processor).
Can anyone show me the way to test the interaction if we don't have the full processor, the BFM and also the reference model for the full processor.
Thank you very much
Verilog full processor is not available now.
But all of other components on the system like AMBA bus, UART, Timer,..., we use designware from Synopsys (so it is available now).
Now we want to test the interaction on the AMBA Bus first (while waiting for the full processor).
Can anyone show me the way to test the interaction if we don't have the full processor, the BFM and also the reference model for the full processor.
Thank you very much