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ALU 4 bit data multiplexer

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jessilen

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View attachment 6E5Z1101_Verlilog_Assignement_Guidance_030216.pdf

Hello Everyone, I got this assignment as attached, but I am completely useless in Verilog.

The codes that I have so far:

Template


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module ALU_4bit_template(clock_50,key0,key1,hex5,hex4,sw0,sw1,sw2,sw3,sw4,sw5,sw6,led_clk_reg,led_clr, led_sw, led_add_cout, led_sub_cout); //(don't change)
 
// Define Port Declarations  with pin numbers (don't change)
(* chip_pin = "E22"*) output led_clr;           // LED G1
(* chip_pin = "E21"*) output led_clk_reg;   // LED G0
(* chip_pin = "E25"*) output led_add_cout;  // LED G2
(* chip_pin = "E24"*) output led_sub_cout;  // LED G3
 
(* chip_pin = "J19,E18,F18,F21,E19,F19,G19"*) output [6:0]led_sw; // LED R0 - R6
 
/////////////////////////////////////////////////////////////////////////////////////
// you need to add the pin numbesr to these ones!
input clock_50;
input key0;
input key1;
 
input sw0;
input sw1;
input sw2;
input sw3;
input sw4;
input sw5;
input sw6;
output [6:0] hex4;
output [6:0] hex5;
/////////////////////////////////////////////////////////////////////////////////////
// define internal signals (don't change)
wire clk_reg, nclr;
wire [3:0] aux_bus, acc_bus;
wire [2:0] instr_bus;
 
/////////////////////////////////////////////////////////////////////////////////////
// define your own internal wires here
 
 
 
/////////////////////////////////////////////////////////////////////////////////////
// connect switches to aux bus (don't change)
assign aux_bus[0] = sw0;
assign aux_bus[1] = sw1;
assign aux_bus[2] = sw2;
assign aux_bus[3] = sw3;
// connect switches to instr_bus (don't change)
assign instr_bus[0] = sw4;
assign instr_bus[1] = sw5;
assign instr_bus[2] = sw6;   
// connect leds to switches and keys (don't change)
assign led_sw[0] = sw0;
assign led_sw[1] = sw1;
assign led_sw[2] = sw2;
assign led_sw[3] = sw3;
assign led_sw[4] = sw4;
assign led_sw[5] = sw5;
assign led_sw[6] = sw6;
assign nclr = key1;
assign led_clk_reg = clk_reg;
assign led_clr = nclr;
/////////////////////////////////////////////////////////////////////////////////////
// define clk_gen 
clk_gen u1 (.clk(clock_50),.nclr(nclr), .sw_press(key0),.clk_reg(clk_reg));
/////////////////////////////////////////////////////////////////////////////////////
// define 7 seg drivers for hex4, hex5 (don't change)
seven_seg u2(.data_in(acc_bus), .data_out(hex4));       // acc_bus output
seven_seg u3(.data_in(aux_bus), .data_out(hex5));       // aux_bus output
 
/////////////////////////////////////////////////////////////////////////////////////
// define your logic units here
// Note connect the cout signal from the adder and subtraction unit to the following signals  led_add_cout, led_sub_cout respectively. 
// To set a signal to logic-1 you can use 1’b1, or to logic-0 you can use 1’b0.
 
 
/////////////////////////////////////////////////////////////////////////////////////
// define your mux here
                                    
/////////////////////////////////////////////////////////////////////////////////////
// define acc register here
 
endmodule





clk_gen:

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module clk_gen(clk,nclr, sw_press,clk_reg);
 
input clk, nclr,sw_press; 
output clk_reg;
wire [19:0] clk_divider;
 
// define 20 bit up counter to act as a clock divider to divide down 50MHz to slow freq down arouns 48HZ... 50MHZ / 2pow20
counter_up_nbit #(.n(20)) u1(.q(clk_divider),.clk(clk),.nclr(nclr));
fsm u2(.clk(clk_divider[19]), .nclr(nclr), .sw_press(sw_press),.pulse(clk_reg));
 
endmodule



counter_up_nbit:

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module counter_up_nbit(q,clk,nclr);
parameter n = 4;  // output width in bits (default is 4)
input clk,nclr; // nclr = 0, q = 0
output [n-1:0]q;
 
reg [n-1:0]q;
  
always @ ( posedge clk or negedge nclr)
begin
       if(nclr == 1'b0) 
                begin
              q <=  {n{1'b0}};  // set n bits to 0 (verilog 2001)
                end
        else
                begin
                q <= q + 1;
            end
end
endmodule



d_type:

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module d_type (d ,clk,nclr,q );
input d, clk, nclr ; 
output q;
reg q;
 
always @ (posedge clk or negedge nclr) // use negedge as switches have pull ups. 
if (~nclr)  // if nclr = 0, then q = 0
    begin
    q <= 1'b0;
    end  
else // if nclr = 1, then q = d
    begin
    q <= d;
    end
 
endmodule




I'm so confused ! Any help would be appreciated widely !
 
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Ugh, Verilog '95 port syntax. C-style syntax came out in Verilog 2001 and IS supported by every Verilog synthesis/simulation tool you would ever want to use (if it isn't supported why would you even use the tool?).

You've got a start with the code already so what exactly confuses you? You still need to implement the other functions. It's implied by the table you need to make modules with the names shown, with testbenches for each one. Though with the code above you didn't seem to use any of the "suggested" names. You might want to read your assignment description.

Be careful with the ordering of the mux select as the LOAD input is on the bottom, but the code for it is 000. Maybe the prof is trying to trick the students.
 

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