Altium design - polygon pour problem with via

[wildone_za]

Hi All,

I have recently moved from Protel 99SE to Altium Winter 09. I have an issue when doing a polygon pour over the top and bottom layers. It is a simple PCB and I am doing the board without a schematic - thus no net lists. I have created a manual net called GND and changed the necessary pads of components connect to NET - GND. So far so good - exactly the same as 99SE. I then do a polygon pour on the top and bottom connected to net GND - again works as expected. As the PCB has some RF, I stitch the top and bottom layers with vias, which then are on the GND net. If I have to re-pour either the top or the bottom polygon, the vias that were solidly connected to the polygon plane, now have themal relief. This did not happen in 99SE. I have tried Design -> Rules -> PolygonConnect to eliminate this, but then my SMD components do not have thermal relief.

I am sure there must be a simple way to prevent vias from having thermal relief, but I can't seem to find the solution.

Any suggestions?

Thanks in advance.

 

[loosemoose]

you need to set up a design rule for vias to connect directly to copper. It's under polygon connect style.

 

[wildone_za]

Thanks - I managed to create the rule and now all is well again.