Newbie level 4
I've got a component which requires a fairly hefty heatsink pour on the bottom layer. Next to it I've got a couple of high voltage traces that I want to keep well clear of the heatsink polygon. I want to make the poly as big as possible, so instead of manually stepping around the traces in question I just gave them a 1mm clearance rule. This works fine - creates a nice neat cutout around them. The problem is I don't want solder mask on this heatsink, so I copied the poly and pasted onto the bottom solder layer. Since the bottom solder is not an electrical layer, the rules don't apply to it, and the poly goes right over the vias in the HV tracks (see attached image). With no mask there, the solder could bridge over to the via and cause much bigger problems. I know it's unlikely with a 1mm gap, but I've got other locations with the same problem with 0.2mm gap. I've tried naming the polygon, and giving it a net and making clearance rules for those but nothing seems to work. I've also tried copying it from the bottom layer and pasting to the solder mask without repouring, but the primitives stay on the bottom copper layer until you repour it. Short of manually laying it out, is there any way to apply clearance rules to polygons on non-signal layers?