[SOLVED] Alternative to $finish systemverilog

[BartlebyScrivener]

For my test bench, once a certain condition is met the testing is finished. At the moment, I have written in the code and if statement to check for the condition, followed by $finish. When I want to test, I type run 100ns, hoping that 100ns will be enough. If not, I have to keep hitting run 100ns till it finishes.

When it finishes, it seems severe... In modelsim, I get asking me if I am sure I want to finish, which if I click yes, will close modelsim!

Is there a neater way to just run a test bench till completion without closing modlesim?

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I just found run -all which works, so all I want now is for it to not try and close modelsim when it finishes.

Thansk

 

[BartlebyScrivener]

stop(1) seems to work, but it still crashes my scripts.

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I added

onbreak {resume}

to my scripts and this solved it