Alternative(optimum) usage of memory in FPGA.

[ismailov-e]

Hi!
Are all registers, array or matrix of registers are uses DRAM memory?
I have used a 2D array of register with 32 bit cells, and the utilization exceed maximum FPGA's (Zynq7020) possibilities(LUT and FF), but BRAM,MEMORY LUT, DUFG has shown less usage.
Is there any solution to use BRAM?

 

[amit.kumar11]

Hi,


You can declare a BRAM memory for that. It will be there in ip initialization section and it will be in built in FPGA. Basically all the register , array etc wont use DRAM memory automatically. you have to declare them specifically to BRAM.



AMit

 

[FvM]

Most likely, your design ignored the requirements for block RAM synthesis, so that the memory has been implemented in general registers instead. The compilation report should contain a respective warning.

Not clear which DRAM you refer to?

 

[ads-ee]

Are all registers, array or matrix of registers are uses DRAM memory?

The memory in an FPGA is NOT made up of DRAM (Dynamic RAM) it consists of SRAM (Static RAM) for memory and Flip-Flops for registers.

 

[ismailov-e]

The memory in an FPGA is NOT made up of DRAM (Dynamic RAM) it consists of SRAM (Static RAM) for memory and Flip-Flops for registers.

https://www.xilinx.com/support/docu...M5.9.55876.Heading2.ROM.HDL.Coding.Techniques
But I found here: Vivado synthesis can interpret various ram coding styles, and maps them into Distributed
RAMs or Block RAMs.

- - - Updated - - -

Also I found this:

---

Code Verilog - [expand]
1
(* ram_style = "block" *) reg [data_size-1:0] myrom [2**addr_size-1:0];

---

Am I need in Synthesis settings to set -max_bram to some value (by default is -1)

- - - Updated - - -

I have tried to add "ram_style" but no BRAM utilization after synthesis.

 

[TrickyDicky]

USing the ram_style attribute is not going to work unless your code infers rams properly. From your first post, it sounds like your code isnt correct. Why not post your code.

 

[ismailov-e]

USing the ram_style attribute is not going to work unless your code infers rams properly. From your first post, it sounds like your code isnt correct. Why not post your code.

I have declared the 2d array regester as:

---

Code Verilog - [expand]
1
(* ram_style = "block" *) reg [15:0] state_machine [0:state_count][0:96];

---

- - - Updated - - -

I have checked with 1D array and it's works fine(programm below), but with 2D it not.

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
/*
** This example shows the use of the Vivado ram_style attribute
**
** Acceptable values are:
** block : Instructs the tool to infer RAMB type components.
** distributed : Instructs the tool to infer LUT RAMs.
**
******************************************************************/
 
module ram_inf_64x1d_2 (a, dpra, clk, din, we, spo, dpo);
 
    parameter ADDRESSWIDTH = 6;
    parameter BITWIDTH = 1;
    parameter DEPTH = 34;
        
    input clk, din, we;
    input [ADDRESSWIDTH-1:0] a, dpra;
    
    output spo, dpo;
    
    (* ram_style = "block" *)
    reg [BITWIDTH-1:0] ram [DEPTH-1:0];
    reg [ADDRESSWIDTH-1:0] read_dpra; 
    reg [ADDRESSWIDTH-1:0] read_a; 
 
    always @(posedge clk) begin
        if (we) begin
            ram [a] <= din;
        end
        read_a <= a;
        read_dpra <= dpra;
    end
    
    assign spo = ram [read_a];
    assign dpo = ram [read_dpra];
    
    
endmodule

---

 

[FvM]

I won't expect the Xilinx tool to infer 2D RAM, otherwise it should be specified somewhere. But you can easily map 2D to 1D-RAM, just some simple index arithmetics, respectively combining address bits.

 

[ismailov-e]

I tried to use BRAM in custom IP but couldn't. Is there any trick?
In simple source file it is changes.

 

[TrickyDicky]

Why couldnt you? what errors did you get?
If it just didnt work, I suggest you did something wrong - time for a good debug testbench.

 

[ismailov-e]

Why couldnt you? what errors did you get?
If it just didnt work, I suggest you did something wrong - time for a good debug testbench.

As an example above I putted (* ram_style = "block" *) in one of the source file . After synthesis is still using "distributed" not "block" ram (BRAM).
Also i have a question: If i have 3 source files of different slave ports, does this label (* ram_style = "block" *) putted on one of the source file is enough or need to put every source or in the main?

 

[TrickyDicky]

Like I said before, the ramsyle attribute will do nothing if the code is not written correctly to infer a BRAM. So just arbitrarily adding it to some random source code is useless.

 

[ismailov-e]

Like I said before, the ramsyle attribute will do nothing if the code is not written correctly to infer a BRAM. So just arbitrarily adding it to some random source code is useless.

What you mean under the code is not written correctly?

 

[TrickyDicky]

Read this document:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug901-vivado-synthesis.pdf

Page 95

- - - Updated - - -

Read this document:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug901-vivado-synthesis.pdf

Page 95

 

[ads-ee]

You can also take a look at this guys blog about their experiments with inferring block RAM in both Altera and Xilinx using the same exact code.