Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

alternative for variables used in VHDL coding....

Status
Not open for further replies.
W

win2010

Member level 1
Member level 1
Joined
Sep 30, 2010
Messages
35
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Visit site
Activity points
1,605
Is their any why to avoid lengthy variables or signal used in the VHDL.....?
 

Yes, use shorter ones.
But if you have a massive array, not meant to be a memory, your design is probably wrong in the first place.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top