Alternate clock edge detection

[Chaitanya Sai Chandra]

Hi,
I have to design a sequential circuit which is used to detect clock edges alternately, i.e. the even edges should be in an output and odd edges in an output as shown in fig... Can any one suggest me a design to get the output..


https://obrazki.elektroda.pl/2976235700_1390647792.jpg





Thanks in advance..

 

[nickdean1]

How about something like this?

 

[Dan Mills]

Rising edge triggered D type and two and gates?

D type wired as a divide by two with the Q and *Q outputs anded with the clock to give even and odd outputs that are the same width as the clock (There might be a slight glitch due to the prop. delay of the D type).

Nick deans circuit does not match the clock timing and in any case if that is all that is required a simple D type /2 is very much easier.

Regards, Dan.

 

[Chaitanya Sai Chandra]

Rising edge triggered D type and two and gates?

D type wired as a divide by two with the Q and *Q outputs anded with the clock to give even and odd outputs that are the same width as the clock (There might be a slight glitch due to the prop. delay of the D type).

Nick deans circuit does not match the clock timing and in any case if that is all that is required a simple D type /2 is very much easier.

Regards, Dan.

Thank you Dan, Can you be specific about how circuit schematic looks like for a D/2?

 

[Dan Mills]

Google "d type divide by two", it is about as simple as it gets.

Dan.

 

[Chaitanya Sai Chandra]

Google "d type divide by two", it is about as simple as it gets.

Dan.

Thank you Dan :smile: , I got what you suggested. There are glitches as you mentioned. I need this output for a Duty Cycle corrector and I think it's better to avoid the glitches. Is there any way to remove the glitches?? Any how the output looks like this

https://obrazki.elektroda.pl/7519459300_1390802073.png