Altered Adder with binary output

[Eduard Barnoviciu]

Hello , I need your help here with something : I'm in quite a hurry so that's why I don't do it myself :

I have to design a more intricate CLC and I did most part but at the very end I need a circuit that will add up to 11 1-bit signals to a 4-bit output that will give the number of 1s in binary. so for : i0 = 1 , i1=0 , i2=1 , i3 to i10 = 1 , the sum will be 10 and the output will be 1010.

Once again , I cannot use regs, loops or anything that involves memory or a clock signal.

Please help. Thank you

 

[Eduard Barnoviciu]

I can transform all those 11 outputs into 4 2-bit numbers. Now I just need to add them up. HOW please. how. I need palpable code.

 

[rahdirs]

Hi,

Define an unsigned signal & assign the sum of eleven bits to that signal.Later convert it to a std_logic_vector(3 downto 0).
You have your output.

For counting the number of '1' in your output vector,assign it to a signal & add the individual bits of output vector which you could assign to an integer variable

 

[Eduard Barnoviciu]

Too advanced for me , lel. Sorry. I'm at ' logic gate level' right now. Thanks anyway , I do appreciate it.

 

[rahdirs]

I can transform all those 11 outputs into 4 2-bit numbers. Now I just need to add them up. HOW please. how. I need palpable code.

I didn't see this post(post #2) of yours earlier.

Let's start from the basics.
How did you get those 4 2-bit vectors from 11 bit signals ? Can you post any code ?

I suppose you are doing it in VHDL ?

 

[std_match]

Build a "tree" using normal adders. Make pairs of the input signals, add them and pass to the next "stage". In the first stage you need 5 1-bit adders which will generate 5 2-bit numbers. The leftover bit from the first stage can be padded with a '0' an be used directly in the second stage, where you have 3 2-bit adders which will generate 3 3-bit numbers. Continue like this and after the last step you will have a 5-bit result. The highest bit will always be '0', so it can be left unconnected.