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altera ramstyle attribute

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manojkhandelwal

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Iam trying to infer MLABs or M512 etc....for my RAM implementation
But even if i apply the ramstyle attribute at the variable declaration ,RAM is not getting inferred.
Does any one know the reason....
 

K-J

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Iam trying to infer MLABs or M512 etc....for my RAM implementation
But even if i apply the ramstyle attribute at the variable declaration ,RAM is not getting inferred.
Does any one know the reason....
The code that you have written to infer the RAM performs a different function than what can be implemented in the internal memory. My first guess is that you haven't registered the memory outputs before using them. In any case, you should refer to the Altera manual where you will find a section on how to write the code to infer memory properly. That is the code you want to use.

Kevin Jennings
 

manojkhandelwal

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here is the code
Code:
module my_ram( 
                      //Inputs 
                      clk,    //clock 
                      wr_en,  //write enable 
                      rd_en,  //read enable 
                      addr,   //address 
                      data_in,//data in 
  
                      //Output 
                      data_out//data out 
                   ); 
  
  //Parameter Declaration 
  parameter DEPTH = 8; //depth of FIFO 
  parameter  ADDR_BUS_WD = 3; //Address bus width 
  parameter  DATA_BUS_WD = 8; //data bus width 
  
  
  //Inputs Declarations 
  input  clk;                         //Clock 
  input  wr_en;                       //Write Enable 
  input  rd_en;                       //Read Enable 
  input  [ADDR_BUS_WD-1:0] addr;      //Address Width 
  input  [DATA_BUS_WD-1:0] data_in;   //Data Input 
  
  //output Declarations 
  output [DATA_BUS_WD-1:0] data_out;  //Data Output 
  
  //reg Declarations 
  reg [DATA_BUS_WD-1:0] mem [DEPTH-1:0]/*synthesis ramstyle = "MLAB" */;//Memory 
  reg [DATA_BUS_WD-1:0] data_out;      //Data Output 
  
  //Generation of data_out 
  always @(posedge clk) 
    begin : READ_GEN 
      if(rd_en)  data_out <= mem[addr]; 
    end 
       //Generation Writing data into memory 
  always @(posedge clk) 
    begin: WRITE_GEN   
      if(wr_en)  mem[addr] <= data_in; 
    end 
  
  endmodule
 

FvM

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I think, the problem is with the read enable signal. Altera block RAM is registering the read address, it isn't able to register the output as well within a single clock cycle. You can also refer to the Verilog and VHDL design templates in the Quartus editor context menu.
 

j_andr

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make your ram bigger, say 8x512, and try;
with some sets of settings quartus implements small 2d reg
as registers instead of ram;

check also:
settings->analysis & synthesis settings -> more settings -> 'auto ram to logic cell conversion'

and read compilation messages carefully

J.A
 

manojkhandelwal

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There is no such setting as "auto ram to logic cell conversion"
can u give me exact settings that i need to apply in "analysis and synthesis settings"..> "more settings menu"......so that RAM is being inferred
because i personally feel there is a problem out there.

Thanks in advance
 

manojkhandelwal

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snapshot.jpg
Which version are you using?
 

j_andr

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Which version are you using?

9.1 & 11.0, target device stratix2;
both tools implemented correctly your ram ( and both have the setting I mentioned )
check carefully compile messages, quartus produces a warning/info if a ram
is recognized but for any reasons can not be implemented;
and check fitter report - are you sure your 'mem' has been converted into
registers ?
J.A
 

manojkhandelwal

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Sorry for the late response.....i was off my working system,
the above code now maps to MLABs
Hers an asynchronous read ram with reset signal also....
this is not mapping onto an MLABs......actually i need to implement an asynchronous ram with reset as well
Code:
module my_ram(clk,rst_n,wr_n,rd_addr,wr_addr, data_in,  data_out  );


parameter data_width=8;
parameter depth=16;



input                          clk;
input                          rst_n;
input [3 : 0] rd_addr;
input [3 : 0] wr_addr;
input [data_width-1:0]         data_in;
input                          wr_n;

output [data_width-1:0]        data_out;


reg [data_width-1:0]  data_out;

reg [data_width - 1 : 0]  mem1 [depth-1:0] /* synthesis syn_ramstyle = "MLAB" */ ;

wire [data_width - 1 : 0] mem;

integer i;

//MEM implementation - asynchronous		
always @( posedge clk or negedge rst_n )
	begin
   if ( !rst_n )
		begin
    
    for ( i = 0; i < depth; i = i + 1 )
      begin
          mem1[i] <= 0;
      end
		end
   else
    begin
       if (!wr_n  && (wr_addr<=depth-1))
          mem1[wr_addr] <= data_in;
     end 
	end
assign mem = mem1[rd_addr];
  
always @ *
	begin
		if (rd_addr > depth-1)
	  	 data_out = 0;
		else 
		   data_out = mem;
	end

endmodule

Thanks in advance
 

FvM

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actually i need to implement an asynchronous ram with reset as well
If you review the FPGA hardware manual, you'll understand why it can't be implemented in FPGA internal RAM, it's strictly synchronous.
 

manojkhandelwal

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Hi FvM,
in the manual it is given that MLABs can be configured for asynchronous read.....
in my case the write is synchronous and read is asynchronous......

Thanks
manoj
 

FvM

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Yes, MLAB actually means Memory in Logic Array Block. MLAB can work asynchronously as well.

I'm not sure, how MLAB memory is displayed in the synthesis report. I'm not using Stratix III.
 

manojkhandelwal

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So, when it can work asynchronously why not quartus tool infer it for my asynchronous read RAM??????
is it just because of the reset signal?
Iam having hard time working with the quartus tool.....someone please help....

Thanks in advance,
manoj
 

FvM

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Iam having hard time working with the quartus tool.....someone please help....
If you read the compilation messages thoroughly, you'll find the exact reason for not inferring RAM. The respective restriction of MLAB RAM is also discussed in the Quartus software handbook.

Info: Found 1 instances of uninferred RAM logic
Info: RAM logic "mem1" is uninferred due to unsupported read-during-write behavior
 

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